Design Methodology and Timing Considerations for implementing a TDC on a Cyclone V FPGA Target

Abstract

There are hundreds of research publications that theoretically discuss the implementation of Tapped Delay Line based Time to Digital Converters (TDL TDCs) on Field-Programmable Gate Array (FPGA) targets. However, most of these works do not cover the timing issues that will be encountered mostly due to the routing delays. The purpose of this work is to highlight the main timing issues that should be considered when implementing TDCs in FPGA targets and propose practical approaches to overcome these issues. As a study case, a full design methodology of a TDC on a Cyclone V FPGA target is presented in this work.

Calibration Methods for Time-to-Digital Converters

“…The coarse TDC is a simple counter and the fine TDC is a TDL with 256 delay elements. The total delay of the TDL is 5 ns distributed on the delay elements with the same profile of the time distribution along a real TDL implemented on a Cyclone V FPGA [11].…”

“…In general, high-resolution TDCs can be built as Application-Specific Integrated Circuits (ASICs) [9]. However, for many applications, it can be better to implement the TDC on field-programmable gate arrays (FPGAs) due to the flexibility and reconfigurability, as well as the short development time of these circuits [10][11][12]. Moreover, the integration of hard processor systems in System-on-Chip FPGA (SoC-FPGA) kits allows performing an on-chip downstream processing such as a post-calibration process [11].…”

High precision calibration method for asynchronous time-to-digital converters

“…Each simulated TDC has 256 delay elements and a total delay of 5 ns. Furthermore, the time distribution profile of the simulated TDCs is similar to that of a real TDC implemented on a Cyclone V FPGA kit following the methodology explained in [6]. Firstly, in order to build the LUTs of the bin-by-bin calibration and the calibration tables of the matrix calibration, a code density test is performed by simulating 10 7 random events, with a start and stop arrival times uniformly distributed over the FSR of the start and stop TDCs.…”

“…In our case, this equation gives about 0.005 LSB. In the next simulation, start and stop fine TDCs of 256 delay elements is simulated using the time distribution of a real asynchronous TDC implemented on a Cyclone V SoC-FPGA [6]. A code density test is simulated to the LUTs and the calibration tables in the same way as in the previous simulation.…”

“…In general, application-specific integrated circuits (ASICs) are high-performance solutions to build high-resolution TDCs. However, field-programmable gate array (FPGA) can be a better choice for many applications because of their flexibility and short development time [5][6][7]. Furthermore, system-onchip FPGA (SoC-FPGA) kits integrate a hard processor system with FPGA fabric which enables the efficient integration of a downstream processing such as a post calibration process [6].…”