Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash

3D NAND Flash Architectures

“…4.31 Schematic diagram of 3DVG NAND using island-gate SSL decoding method Chang et al 2012) 4.5.3 Split-Page 3DVG Design (Chen et al 2012a;Hung et al 2012;Hsieh et al 2013) In (B), the overlay concern of island-gate SSL device with BL limits the BL pitch scaling. A split-page 3DVG (Chen et al 2012a;Hung et al 2012;Hsieh et al 2013) is proposed to relax the process issue, as shown in Fig. 4.33.…”

3D VG-Type NAND Flash Memories

“…For example, holes injection during erasing may lower the V TH of the select transistor. If V TH is lowered, then it 14 Simplified 2 layer split page VG NAND [28] is not possible to properly isolate the strings during self-boosting (programming), thus causing failures. To avoid the malfunction, it is necessary to properly bias the select transistor for deselection, by using slightly negative voltages.…”

“…Figure 7.18 shows a detailed timing diagram of the read phase with forward voltage sensing. To avoid "local self-boosting" at the cells between SSL and selected WL, that may lead to hot-carrier induced read disturb, a proper discharge of the channel is done by pulsing SSL during wordlines turn on [28]. The selected wordline is biased slightly negative during the read phase.…”

“…The proposed layer-aware read method uses reverse read with different judging level for each bitline, to compensate for the layer differences. Figure 7.19 shows a schematic example of the reverse-read sensing with multi V TH reading [28]. BL compensation consists in biasing the BLCLAMP transistors of the page buffer at a proper voltage, depending on the layer being read.…”

“…Forward read sensing can be used also in 3D NAND; the Flash string must be properly biased in order to read out the current Fig. 7.16 2-layers structure example (2 units) [28] value of the selected cell. The forward-read sensing method is not described here but is deeply studied in literature [30].…”