Design guidelines for high-speed Transmission-gate latches: Analysis and comparison

Belaidžio ryšio siųstuvų-imtuvų filtrų savitestavimo ir autokalibravimo metodų sukūrimas ir tyrimas

“…4.10 pav.) (Palumbo, Pennisi 2008). Lygiagrečiai jungiant NMOP ir PMOP tranzistorius, tranzistoriams veikiant tiesinėje srityje bei neatsižvelgiant į tranzistorių matmenis, ekvivalentinė grandinės varža apskaičiuojama pagal:…”

65nm TGMS flipflops for High Speed Design Standards

“…The parameter has to be minimized to reduce the influence of FF timing on pipeline speed performances. Thus, for FF speed [14]- [17] it represents the actual figure of merit. As shown in Fig.2, the effect on T CK-Q and T D-Q are opposite on decreasing T D-CK, the former one increases whereas the latter one initially decreases [2].For this reason minimum T D-CK is obtained by defining the setup time tsetup as the optimum T D-CK.…”

“…Small area occupation, charging and discharging of few internal nodes and the absence of pre-charge are its features. In energy efficient microprocessors [14]- [17] TGMS FFs can be used because all of the above factors lead to a small dissipation. In high-speed environment guidelines for design of TGMS FFs is the focus of this paper by means of a reconsideration of the classical LE approach.…”

A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

“…The expression relating the absolute gate capacitance ( C GATE ) in terms of fF (femtofarads) and absolute transistor width ( W ) in terms of nanometers (nm) obtained at 180 nm process node by fitting simulation data [ 30 ] is given as LE method states that the optimized delay D of a path of N cascaded stages is where G , B , H ( = C L / C in ) are the logical effort, branching effort, and electrical effort while P , F (= GBH ) and C L are parasitic delay, path effort, and final load capacitance, respectively. One has the following: From ( 2 ) and ( 4 ), where t represents the relative delay increment with respect to parasitic delay.…”