Design for testability using behavioral models

“…1, is modeled in the Saber RD tool to verify the fault-isolation method. Recently, Saber RD has drawn attention for the simulation of fault in low voltage analog circuitry by emulating the characteristics of actual devices [31], [32]. The platform simulates faults in COOL MOS-based converters [33].…”

Section: Introductionmentioning

confidence: 99%

Fault-Tolerant Control and Isolation Method for NPC-Based AFEC Using Series-Connected 10kV SiC MOSFETs

2022

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Power Conditioning Systems (PCS) based on three-level converters with series-connected 10kV SiC MOSFETs have gained popularity for medium voltage applications with the increase in distributed energy sources. With the use of Silicon Carbide (SiC), a wide bandgap semiconductor composed of Silicon (Si) and Carbon (C), MOSFET increases in power electronics application due to higher switching frequency operations. A high switching frequency such as 10 kHz or more leads to a reduction in magnetic components' size and the PCS structure's size. Therefore, the smaller, modular, and lightweight PCS can be attained for micro-grid integration, EV charging, or high inertia-dominated power grid applications. The three-level NPC (3L-NPC) inverter using series-connected 10kV SiC MOSFET is a suitable topology for coupling the PCS with the medium-voltage utility grid. The converter's pole sustainability increases with the two series-connected switches, yet the switches are still sensitive and prone to malfunction under various environmental and mechanical causes. Therefore, a meticulous fault isolation and coordination design may be necessary for the front-end converter for possible switch faults in the converter poles. A well-designed fault-tolerant controller may sustain the converter operation under fault conditions while protecting the healthy parts of the converter. Besides, it minimizes the harmful effects of fault on the grid side and increases the system availability. This paper analyzes short and open circuit switch faults that might occur in the PCS. Accordingly, a fault-tolerant method and a fault isolation method are proposed. The proposed methods are verified with Saber™ and the Real-Time Digital Simulator simulation platforms.

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“…The package has been installed and is expected to cover a variety of simulation needs related to both design and testing of complex systems, such as high-speed ADC's. Some results on the application of SABER for the testability of analog circuits, are presented elsewhere [3].…”

Section: Simulation Environmentmentioning

confidence: 99%

“…Deviation from desired behavior has to be traced to the existence of an error within the circuit. Testing of analog systems creates particular problems since it may be impossible to probe internal circuit nodes without disturbing global operation [3]. Internal signals often have to be deduced from the relationship between other signals that can be monitored.…”

Section: Introductionmentioning

confidence: 99%

Bridging the gap between design and testing of analog integrated circuits

Soenen

VanPeteghem

Liu

et al.

7th IEEE Conference on Instrumentation and Measurement Technology

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An i m p o r t a n t problem associated with analog and mixed analog/digital VLSI design, has been the lack of a systematic approach t o t h e design and testing of such integrated s y s t e m s . This paper describes a computer environment that brings t h e diflerent design aspects close19 together. It has been used successfully t o analyze the performance of high-speed, flash Analog/Digital converters.

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Design for testability using behavioral models

Cited by 16 publications

References 9 publications

DFT architecture for a dynamic fault model of the embedded mask ROM of SOC

DFT architecture for a dynamic fault model of the embedded mask ROM of SOC

Fault-Tolerant Control and Isolation Method for NPC-Based AFEC Using Series-Connected 10kV SiC MOSFETs

Bridging the gap between design and testing of analog integrated circuits

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