Design for Testability—A Survey

Williams, Stefan B.; Parker,

doi:10.1109/tc.1982.1675879

Cited by 253 publications

(37 citation statements)

References 57 publications

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“…The structured approach for testability was introduced to allow DFT engineers to follow a systematic or established process for improving the testability of a design [3]. A structured DFT technique can be easily incorporated and budgeted for as part of the design flow and can yield the desired results.…”

Section: Structured Approachmentioning

confidence: 99%

Scan Insertion on Multi Clock Design in Modern SOC's

2017

IJSR

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Section: Structured Approachmentioning

confidence: 99%

Scan Insertion on Multi Clock Design in Modern SOC's

2017

IJSR

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“…The next problem is deriving techniques for testability design. A comprehensive survey of these techniques is given in [GRAS80] and [WILL82]. Most of them are of an ad hoc nature, presented either as general guidelines, or hard and fast rules.…”

Section: Testingmentioning

confidence: 99%

The Complexity of Design Automation Problems

Sahni¹,

Bhatt²,

Raghavan³

1988

Handbook of Advanced Semiconductor Technology and Computer Systems

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This paper reviews several problems that arise in the area of design automation. Most of these problems are shown to be NP-hard. Further, it is unlikely that any of these problems can be solved by fast approximation algorithms that guarantee solutions that are always within some fixed relative error of the optimal solution value. This points out the importance of heuristics and other tools to obtain algorithms that perform well on the problem instances of interest.

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“…To accelerate test generation, improve fault coverage and reduce test application time (TAT), the circuit is modified. The circuit modification process during the design phase is called Design For Testability (DFT) [2], [3]. Many ad hoc and algorithmic DFT techniques have been proposed.…”

mentioning

confidence: 99%