Design-for-Manufacture for Multigate Oxide CMOS Process

Lin, Qi; Ma, Mei; Vo, T.; Fan, Jenny; Wu, Xin; Li, R.; Li, Xiaoyü

doi:10.1109/tsm.2007.913190

Cited by 1 publication

(1 citation statement)

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“…These combinations have a triple-gate oxide and it is not manufacturing friendly due to an additional mask penalty, between +1 mask for the gate oxide process only, and up to +8 masks for the case V t and SDE implants also need to be separated. In addition, the complexity of having an oxide-strip at a very small window, the additional thermal budget, and the fact that there are two different gates with a close thickness target are problematic due to the oxidation kinetics [25]. However, it was successfully developed for 28 nm technology, having gate oxides thickness of 16A for Low Power Standby (1.1 V) and 13.5 A for Low Power (0.8 V) [26].…”

Section: Leakage Reduction In Transistor Level-cmos and Srammentioning

confidence: 99%

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Shauly

2012

JLPEA

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Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed

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Section: Leakage Reduction In Transistor Level-cmos and Srammentioning

confidence: 99%

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Shauly

2012

JLPEA

View full text Add to dashboard Cite

show abstract

Design-for-Manufacture for Multigate Oxide CMOS Process

Cited by 1 publication

References 5 publications

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

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