Design for diagnosability guidelines

Ungar, Louis Y.

doi:10.1109/autest.2007.4374195

Cited by 7 publications

(1 citation statement)

References 5 publications

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“…It must be noted that the proposed method is aiming toward the estimation of the fault coverage for a given fault set. On the other hand, testability, as defined by the Testability Management Action Group, is the property of a circuit to be easily tested by using controllable and observable signal nodes buried within the circuit [21]. Thus, testability analysis copes with the problem following a different perspective.…”

Section: Resultsmentioning

confidence: 99%

Improved analogue fault coverage estimation using probabilistic analysis

Papakostas

Hatzopoulos

2009

Circuit Theory & Apps

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SUMMARYA method for fault detection probability estimation using statistical multi-parameter circuit simulation is proposed, in order to check circuits for which double or multiple analogue measurements are utilized. Theoretical analysis for the estimation of the fault coverage is given, based on conditional probability calculations. The proposed method can be applied for both test measurement and input stimulus selection. Simulation results from the application of the method on typical analogue circuits-filter and amplifierare given, showing a sufficient improvement over the fault coverage achieved by single measurements.

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Section: Resultsmentioning

confidence: 99%

Improved analogue fault coverage estimation using probabilistic analysis

Papakostas

Hatzopoulos

2009

Circuit Theory & Apps

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The economics of harm prevention through Design for Testability

Ungar

2008

2008 Ieee Autotestcon

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Simplified metrics for evaluating designs for testability

Ungar

Davidson

2009

2009 Ieee Autotestcon

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Design for Testability (DFT) evaluation is quite complex and circuit dependent. To simplify the analysis and to apply the methodology more generally to different circuit types and different levels of assembly, we focus our efforts on identifying areas of poor testability. We introduce metrics we call Sensitized Path Oriented Testability Scoring TM or SPOTS TM , performed at all points where failure modes are to be detected and diagnosed, to spot poor testability. Once the problem is identified early in the design stage, especially when it is correlated with a circuit node and a failure mode, the remedy needed to correct the problem through DFT can be quite practical. SPOTS measures four testability attributescontrollability, distinguishability, test resource costs, and test escapes due to lack of testability. The metrics simplify previous testability techniques, by utilizing sensitized paths to measure circuit controllability. The use of sensitized paths greatly reduces the analysis required, and while it may not offer validation of testability, it succeeds in highlighting areas that lack testability. Controllability metric (CM) provides a number corresponding to the number of steps required to sensitize a path. Distinguishability metric (DM) measures the difficulty of isolating one fault from others. Test resource cost (RC), includes test program set (TPS) development costs and test equipment requirements, and is expressed in monetary currency. Penalty cost (PC) measures in currency the cost incurred for nodes left untested by escaping detection in tests.Associating each of these metrics to failure modes at each node creates a table that reveals where testability problems exist. Designers and testability analysts can work together to resolve them either by altering the fault detection and isolation requirements, improving test resources and/or redesigning the unit under test (UUT). This form of analysis is simpler to use and is applicable to any level of assembly -IC, board or system. It can even be utilized by those procuring commercial off the shelf (COTS) products to compare support costs for competing products.

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Design for diagnosability guidelines

Cited by 7 publications

References 5 publications

Improved analogue fault coverage estimation using probabilistic analysis

Improved analogue fault coverage estimation using probabilistic analysis

The economics of harm prevention through Design for Testability

Simplified metrics for evaluating designs for testability

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