Design Flow for Radhard TMR Flip-Flops

Petrović, Vladimir; Krstić, Miroslav

doi:10.1109/ddecs.2015.65

Cited by 35 publications

(17 citation statements)

References 6 publications

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“…Fig 2 shows the most critical 5 % of the flip-flops for one of the randomly created clock networks, ranked by the individual functional failure rate. In case of selective mitigation these flip-flops should be considered for hardening with the ∆-TMR technique [17].…”

Section: B Results For Sets In the Clock Distribution Networkmentioning

confidence: 99%

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Lange

Glorieux

Alexandrescu

et al. 2019

2019 14th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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With technology scaling, lower supply voltages, and higher operating frequencies clock distribution networks become more and more vulnerable to transients faults. These faults can cause circuit-wide effects and thus, significantly contribute to the functional failure rate of the circuit. This paper proposes a methodology to analyse how the functional behaviour is affected by Single-Event Transients in the clock distribution network. The approach is based on logic-level simulation and thus, only uses the register-transfer level description of a design. Therefore, a fault model is proposed which implements the main effects due to radiation-induced transients in the clock network. This fault model enables the computation of the functional failure rate caused by Single-Event Transients for each individual clock buffer, as well as the complete network. Further, it allows the identification of the most vulnerable flip-flops related to Single-Event Transients in the clock network.The proposed methodology is applied in a practical example and a fault injection campaign is performed. In order to evaluate the impact of Single-Event Transients in clock distribution networks, the obtained functional failure rate is compared to the error rate caused by Single-Event Upsets in the sequential logic.

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Section: B Results For Sets In the Clock Distribution Networkmentioning

confidence: 99%

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Lange

Glorieux

Alexandrescu

et al. 2019

2019 14th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…Further considerations include reduced operating and threshold voltage that, together with higher feature density, will lead to lower SEU immunity. Defect mitigation commands the highest effort in the first instance [31] but a number of approaches nonetheless been reported in recent years as summarised in Table IX. nMR has also been incorporated within FPGA configurations at the block level [65], extended to fine-grained gate redundancy by a method closely related to quadded logic [60] and ultimately appearing at the transistor level via N-modulo redundancy (nMR) [66] and most commonly TMR implementations [67]. A further variation involves scrubbing in which the configuration is periodically refreshed from a golden bitstream [68].…”

Section: A Passive Methodsmentioning

confidence: 99%

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

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Self-engineering systems that are capable of repairing themselves in-situ without the need for human decision (or intervention) could be used to achieve zero-maintenance. This philosophy is synonymous to the way in which the human body heals and repairs itself up to a point. This article synthesises issues related to an emerging area of self-healing technologies that links software and hardware mitigations strategies. Efforts are concentrated on built-in detection, masking and active mitigation that comprises self-recovery or self-repair capability, and has a focus on system resilience and recovering from fault events. Design techniques are critically reviewed to clarify the role of fault coverage, resource allocation and fault awareness, set in the context of existing and emerging printable/nanoscale manufacturing processes. The analysis presents new opportunities to form a view on the research required for a successful integration of zero-maintenance. Finally, the potential cost benefits and future trends are enumerated.

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“…These are hardware Triple Modular Redundancy (TMR) [10], Junction Isolated Common Gates (JICG) [11], Dual Interlocked Storage Cell (DICE) [12], etc. They have been studied intensely and already experimentally proved their fault-tolerance to radiation influence [10], [11], [12]. The resistance of the radiation hardened gates against manipulation as well their resistance against side channel analysis attacks have to be investigated.…”

Section: Metal Fillers As Low Cost Countermeasurementioning

confidence: 99%

“…However implementation of such countermeasures usually requires hardware redundancy, e.g. triplication in TMR [10], doubling in JICG [11], doubling or triplication in DICE cells [12]. Due to this fact, such countermeasures require increased area on a silicon die compared to non-radiation hardened implementations.…”

Section: Metal Fillers As Low Cost Countermeasurementioning

confidence: 99%

Metal Fillers as Potential Low Cost Countermeasure against Optical Fault Injection Attacks

Petryk

Dyka

Katzer

et al. 2020

2020 IEEE East-West Design &Amp; Test Symposium (EWDTS)

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Physically accessible devices such as sensor nodes in Wireless Sensor Networks or "smart" devices in the Internet of Things have to be resistant to a broad spectrum of physical attacks, for example to Side Channel Analysis and to Fault Injection attacks. In this work we concentrate on the vulnerability of ASICs to precise optical Fault Injection attacks. Here we propose to use metal fillers as potential low-cost countermeasure that may be effective against a broad spectrum of physical attacks. In our future work we plan to evaluate different methods of metal fillers placement, to select an effective one and to integrate it as additional design rules into automated design flows.

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Design Flow for Radhard TMR Flip-Flops

Cited by 35 publications

References 6 publications

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

Metal Fillers as Potential Low Cost Countermeasure against Optical Fault Injection Attacks

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