Design Considerations for Memristive Crossbar Physical Unclonable Functions

Abstract

Hardware security has emerged as a field concerned with issues such as integrated circuit (IC) counterfeiting, cloning, piracy, and reverse engineering. Physical unclonable functions (PUF) are hardware security primitives useful for mitigating such issues by providing hardware-specific fingerprints based on intrinsic process variations within individual IC implementations. As technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies, such as memristors or RRAMs (resistive random-access memory), have become interesting options for emerging computing systems. In this article, using a comprehensive temperature dependent model of an HfO x (hafnium-oxide) memristor, based on experimental measurements, we explore the best region of operation for a memristive crossbar PUF (XbarPUF). The design considered also employs XORing and a column shuffling technique to improve reliability and resilience to machine learning attacks. We present a detailed analysis for the noise margin and discuss the scalability of the XbarPUF structure. Finally, we present results for estimates of area, power, and delay alongside security performance metrics to analyze the strengths and weaknesses of the XbarPUF. Our XbarPUF exhibits nearly ideal (near 50%) uniqueness, bit-aliasing and uniformity, good reliability of 90% and up (with 100% being ideal), a very small footprint, and low average power consumption ≈104μW.

Optimization of Memristive Crossbar Array for Physical Unclonable Function Applications

“…Later in [17] the Xbar PUF performance evaluation was done with slight improvement in the design using bipolar resistive switching of memristors and a 2-D crossbar array was proposed. The design was further improved in [18] by adding nonlinearities in the response by incorporating column swapping technique in the Xbar and processing the output through exclusive OR gate (XORing). The comparative performance evaluation and resistance to ML attacks like Logistic Regression (LR) and Support Vector Machine (SVM) was done in [19].…”

“…The comparative performance evaluation and resistance to ML attacks like Logistic Regression (LR) and Support Vector Machine (SVM) was done in [19]. All of the above PUF architectures were based on delay based arbiter PUF [18]. A general framework of logical and filter based approximation attacks on Arbiter PUFs is discussed in [20].…”

“…To counter these Machine Learning based approximation attacks a large crossbar size capable of generating large CRP space or some challenge obfuscation strategy [21] is needed. It was analyzed in [18] that if more number of rows are added in the memristive crossbar then the voltage resolution at the load resistance will be finer, requiring precise sense circuitry. A sense amplifier is also proposed for this purpose in [22].…”

“…All of the above techniques used the memristors with low OFF/ON ratio (10 to 100) and less noise margin. In [18] the load resistance optimization and its impact was slightly discussed for a 32 × 2 Xbar in the light of 2% variations in the load resistance. The NM was found out to be 40%, which means a read voltage signal of 500mV will translate to 200mV drop at the load resistance.…”

“…The NM was found out to be 40%, which means a read voltage signal of 500mV will translate to 200mV drop at the load resistance. It is also stated in [18] that with the increase in Xbar size, this voltage will be further reduced and a sense amplification circuitry will be required.…”