2018
DOI: 10.1109/tvlsi.2018.2812700
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Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic

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Cited by 4 publications
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“…Some of the ways to reduce the leakage power are clock and power gates, transistor stacking, adaptive body biasing, etc. [5,16,17].…”
mentioning
confidence: 99%
“…Some of the ways to reduce the leakage power are clock and power gates, transistor stacking, adaptive body biasing, etc. [5,16,17].…”
mentioning
confidence: 99%