Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

Ritter, Philipp; Tual, Stephane Le; Allard, Bruno; Möller, Michael

doi:10.1109/jssc.2014.2316231

Cited by 22 publications

(8 citation statements)

References 8 publications

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“…This results in a low THD and a related ENoB in excess of the targeted 8-bit resolution in the frequency range of the first Nyquist band of the driving DACs for differential input amplitudes up to 500 mV (1Vpp). As explained in [12] (see Section III-A), high bias currents of 2 × 4 mA and 2 × 14 mA are used for the first and second EF-pair to sustain the inherently high linearity of the EFs at high frequencies for driving the capacitive input impedance of TAS1,2. For the EF-pairs at the clock input, high bias currents of 2 × 8 mA and 2 × 20 mA are chosen to drive the high capacitive load represented by the four SEL1,2 CSs.…”

Section: Circuit Concept and Linearity Considerationsmentioning

confidence: 99%

Resolution-Related Design Considerations for a 120-GS/s 8-bit 2:1 Analog Multiplexer in SiGe-BiCMOS Technology

Collisi

Möller

2021

IEEE J. Solid-State Circuits

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This article presents a 120-GS/s 2:1 8-bit analog multiplexer (AMUX) in SiGe-Bipolar CMOS (BiCMOS) technology that exhibits the highest effective resolution reported for an AMUX in any kind of semiconductor technology. This article presents the design considerations that have led to this high resolution. In particular, it contains a discussion on the choice of an AMUX circuit concept to support high linearity. A frequency-domain explanatory model for the signal contribution to the effective number of bits (ENoB) in the presence of mismatch errors is presented and applied to the analysis of timing and signal gain mismatch in the AMUX setup. Typical ENoB versus frequency characteristics were identified and utilized to speed up ENoB simulations and to develop calibration procedures for the different mismatch types in the AMUX setup. The results of the analysis and the performance of the AMUX in the calibrated setup were proven by measurement results. Index Terms-Analog multiplexer (AMUX), digital-toanalog-converter (DAC), effective number of bits (ENoB), high speed, linearity explanatory model, SiGe-Bipolar CMOS (BiCMOS).

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Section: Circuit Concept and Linearity Considerationsmentioning

confidence: 99%

Resolution-Related Design Considerations for a 120-GS/s 8-bit 2:1 Analog Multiplexer in SiGe-BiCMOS Technology

Collisi

Möller

2021

IEEE J. Solid-State Circuits

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“…In this rential pair driven ifferential pair is rs (M5 -M6) and 1) which serve as s feedback loop is ined by M2 -M3, and M10 form a provided by M5 stage output is e PMOS amplifier is a basic CMOS tic [4] sed multiplexer coder, 2 x 1 atic [5] C. Regenerative Buffer This represents the transistor lev two stage simple 2 stage buffer [12 buffer is used to delay a signal a sho signal that has degraded to a poin unintelligible. The resistor string [13] of 2 N switches, the analog output is simpl the resistors at the selected tap.…”

Section: A the Comparator Structurementioning

confidence: 99%

“…[13] In this scheme, comparison processes with all quantization levels correspond to an instant analog input voltage level are done simultaneously during only one cycle of the sampling clock signal. First phase of the sampling clock is for sampling, second phase is for converting and obtaining output binary data [6].This property makes flash ADC as the fastest one among others.…”

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confidence: 99%

Design of a 5-bit, 4.87GS/s, 240µW Flash ADC using a MUX-based decoder with Regenerative Buffer in 45-nm CMOS

Patel¹,

Muralidhara²

2015

2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)

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This paper presents a 5 -bit 4.87GSps Flash ADC design using 45-nm GPDK CMOS technology library. The designed system consists of two main blocks as comparator array and digital decoder. The digital decoder contains 2:1 MUX based 1 -of -N decoder and Regenerative Buffer units. As a result, active die area and the power consumption are reduced in addition to increase in sampling frequency. The power supply voltage range for the overall system is ± 1.8V. The simulation results include maximum power consumption of 0.24 mW. The Conversion time 204p sec, the measured DNL and INL to less than 0.02LSB and 0.1LSB.

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“…High-speed ADCs with moderate resolution are in high demand for applications such as the radar receiver. Although the flash ADC is known as the simplest and fastest architecture, the resolution is limited since the number of comparators increases exponentially with the number of bits, resulting in unacceptable complexity [1][2][3]. In pipelined ADC, large latency is inevitable because of the multiple pipeline stages, and this is undesirable for swift response situations.…”

Section: Introductionmentioning

confidence: 99%

A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

et al. 2019

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A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

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Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

Cited by 22 publications

References 8 publications

Resolution-Related Design Considerations for a 120-GS/s 8-bit 2:1 Analog Multiplexer in SiGe-BiCMOS Technology

Resolution-Related Design Considerations for a 120-GS/s 8-bit 2:1 Analog Multiplexer in SiGe-BiCMOS Technology

Design of a 5-bit, 4.87GS/s, 240µW Flash ADC using a MUX-based decoder with Regenerative Buffer in 45-nm CMOS

A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

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Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

Cited by 22 publications

References 8 publications

Resolution-Related Design Considerations for a 120-GS/s 8-bit 2:1 Analog Multiplexer in SiGe-BiCMOS Technology

Resolution-Related Design Considerations for a 120-GS/s 8-bit 2:1 Analog Multiplexer in SiGe-BiCMOS Technology

Design of a 5-bit, 4.87GS/s, 240&#x00B5;W Flash ADC using a MUX-based decoder with Regenerative Buffer in 45-nm CMOS

A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

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Design of a 5-bit, 4.87GS/s, 240µW Flash ADC using a MUX-based decoder with Regenerative Buffer in 45-nm CMOS