Design Considerations and Residual Offset Analysisfor an Autozero Transconductance Amplifier Topology

Abstract

This paper presents a standard topology autozero transconductance (AZ]) amplifier systematic design flow and performance analysis. This topology uses two differential pairs: one for the signal path and one for offset compensation. A standard 0.6 uim CMOS technology was used and the residual offset resulted about 1 7,uV

An area efficient low offset autozero amplifier design

“…1 [1,2]. The base amplifier, G m1 , can either be connected to the input signal or have its inputs shorted together, via S 2 , S 3 switches.…”

“…The AZ process is composed of two phases: the offset sampling phase and the signal processing phase. [1,2]. During the sampling phase, the amplifier is disconnected from the signal paths and its inputs are shorted together.…”

“…During the signal processing phase, the amplifier is connected to the signal path and the correction voltage measured in the previous phase is applied. A detailed analysis [2] shows that the offset is not totally cancelled but reduced to:…”

“…The charge injection error is proportional to the switch capacitance [see equation (2)] so, for charge injection minimization the switches should be implemented with minimum area transistors. However, during the offset sampling phase, the S/H capacitors are loaded through S 1 and S 4 switches.…”