Design Considerations and Experimental Verification of a 10.5mW 1GS/s Hybrid ADC for Portable Wireless Devices

Zahrai, Seyed Alireza; Zlochisti, Marina; Dortz, Nicolas Le; Onabajo, Marvin

doi:10.1109/iscas.2018.8351660

Cited by 2 publications

(4 citation statements)

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“…After recording the digital output data from the four channels with the logic analyzer, it was evaluated in MATLAB. Detailed measurement results are reported in [33], whereas this section summarizes the key observations that were made during the testing of the example hybrid ADC.…”

Section: Summary Of Measurement Resultsmentioning

confidence: 99%

“…The work in [32,33] exemplified the concept of a subranging time-interleaved architecture by realizing a hybrid flash TI-ADC with four time-interleaved CABS ADCs. This architecture employs a CABS ADC in a time-interleaved hybrid ADC configuration to take advantage of its power efficiency at relatively high speeds compared to conventional SAR ADCs.…”

Section: Architecture Case Studymentioning

confidence: 99%

“…A single-ended illustration of the ADC architecture from [32,33] is displayed in Figure 14. The architecture is a subranging ADC comprised of a 3-bit 1 GS/s flash ADC in the first stage and four time-interleaved 250 MS/s 5-bit CABS ADCs in the second stage.…”

Section: Architecture Case Studymentioning

confidence: 99%

“…This subsection includes measurement setup details and explanations for the hybrid ADC example architecture discussed in Section 4.2 beyond the information in [32,33], which was fabricated in 130-nm CMOS technology and assembled in a TQFP128 package with a ground plane underneath. The full layout of the ADC is shown in Figure 17.…”

Section: Prototype Chip Layout and Testing Considerationsmentioning

confidence: 99%

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Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

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Section: Summary Of Measurement Resultsmentioning

confidence: 99%

Section: Architecture Case Studymentioning

confidence: 99%

Section: Architecture Case Studymentioning

confidence: 99%

Section: Prototype Chip Layout and Testing Considerationsmentioning

confidence: 99%

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