Design, Assembly and Reliability of Large Die (21 x 21mm2) and Fine-pitch (150pm) Cu/Low-K Flip Chip Package

Abstract

underfill materials must be able to offset the CTE mismatch This paper focused on design, assembly and reliability between the silicon chip and organic substrate and at the same assessments of 21 x 21mm2 Cu/Low-K Flip Chip (65nm time, protect the integrity of the Cu/low-K materials from technology) with 150pm bump pitch. Metal redistribution delamination. [4][5] layer (RDL) and polymer encapsulated dicing lane (PEDL) Experimental Procedures were applied to the chip wafer to reduce the shear stress on the 1. Finite Element Modeling Cu/low-K layers and also the strain on the solder bumps. The A two-dimensional plane strain analysis was performed on first level interconnects evaluated were Pb-free the diagonal cross-section of the package with emphasis on (97.5Sn2.5Ag), High-Pb (95Pb5Sn) and Cu-post/95Pb5Sn. thermally induced stress in Cu/low-K layer and inelastic Two different die thicknesses, such as 750 ptm and 300ptm, were~~~~~~~' evlatd Th'lpci sebl fhg-bts energy density range per TC cycle (A\W) in solder bumps. A were evaluated. The flip chip assembly of high-Pb test lag di fli chi pakg ih2 2 di*ie,10t