Design and verification of SPI bus IP core

Abstract

With the development of chip design technology, the complexity of the chip is getting bigger and bigger, and various IP (Intellectual Property) is integrated to form SoC (System on Chip). In order to improve the efficiency of designing SoC, IP reuse technology is often used, so the development of IP has a wide range of significance and use value. The SPI bus is a bus protocol often used in chip communication and has many application scenarios. Therefore, this research mainly develops the SPI bus IP. During the development process, the SPI bus design is carried out, then based on the UVM verification methodology the designed IP has been functionally verified, and finally, a fully functional SPI bus design is obtained.

Design and simulation implementation of SPI protocol interface based on Verilog

“…Basic concepts and characteristics of the SPI protocol. Serial Peripheral Interface (SPI) is a synchronous serial communication protocol used for high-speed full-duplex data transfer between primary and secondary devices [4]. It has many characteristics: there is a master device and one or more slave devices in the communication, and the master device is responsible for controlling the initiation and termination of the communication; Data transmission in communication is synchronized through a shared clock signal, which is generated by the master device; At the same time, it is simple and flexible, SPI protocol communication mode can be configured according to specific needs, can support different data bit width and different communication frequency; The transmitted data frame does not require the address field, and the data is transmitted directly through the data line.…”