The Rapid Single Flux Quantum (RSFQ) circuit is a kind of superconducting digital circuit, having the property of a natural gate-level pipelining synchronous sequential circuit, which demonstrates high energy efficiency and high throughput advantage. We found that the high-throughput and high-speed performance of the RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm, but these are rarely applied to this field. Among the available encryption algorithms, the AES algorithm is an advanced encryption standard algorithm. It is currently the most widely used symmetric cryptography algorithm. In this work, we aim to demonstrate the SubByte operation of an AES-128 algorithm by using RSFQ circuits based on the SIMIT Nb03 process. We design an AES S-box circuit in the RSFQ logic, and compare its operational frequency, power dissipation, and throughput with those of the CMOS-based circuit post-simulated in the same structure. The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz. Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box. Further, we design and fabricate a few typical modules of the S-box. Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.