Design and Verification of AMBA AHB

Giridhar, Perumalla; Choudhury, Priyanka

doi:10.1109/icatiece45860.2019.9063856

Cited by 19 publications

(6 citation statements)

References 2 publications

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“…The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories, and off-chip external memory interfaces with low-power peripheral microcell functions [1].…”

Section: Multi Processors Arbitration Scheme and Signals In Amba Bus ...mentioning

confidence: 99%

“…For example, a locked transfer allows a master to complete a transfer without allowing other masters to access the bus. Similarly, a SPLIT response issued by a SPLIT-capable APB device prevents any master new bus access unless it signals to the arbiter that it is ready to complete the transfer [1].…”

Section: Hgrantx (Bus Grant)mentioning

confidence: 99%

“…Previously in industry single processor, be it internal and external, was used with ASIC and processor had full access to the decanted data, address, control and status signals. So anytime single processor needed access to any targets, it got the control of the bus right away with the grant signal [1]. As the size and complexity of various ASICs and SoCs system have grown to very high to coop with the increased number of hardware operations.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Dual Mode Arbitration Scheme for Multiprocessor Hardware Interface in System-on-Chip

Motakabber,

Rokon,

Alam

et al. 2023

IJEEI

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A processor transforms human needs into hardware operations in any SoC. The single processor was ubiquitous in previous systems. But as chip size, complexity, and speed increase, several processors are used nowadays to handle concurrent operations. To manage requests from several processors, a central hardware block will conduct the arbitration among the processors and allow a processor to access the bus. This paper addresses the multiprocessor arbitration in any System on Chip or ASIC. There are several arbitration algorithms available in the realm of technology, and any system can choose a specific arbitration to implement in hardware based on its own demands. Instead of using one type of arbitration in hardware, this research combined and used two schemes and implemented both possibilities in a hardware dualmode arbiter system to be used in SoC. The proposed dual-mode arbiter was initially hardware modeled using Verilog HDL, then functionalities were verified using industry simulator Cadence and Modelsim, and finally synthesized and implemented using Xilinx XST EDA tool and FPGA device. The AMBA, the industry-standard bus protocol, is being considered for the master processors and the proposed dual-mode arbiter to ensure an efficient hardware interface and to use with any off-the-shelf macro available for the high-tech industry.

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Section: Multi Processors Arbitration Scheme and Signals In Amba Bus ...mentioning

confidence: 99%

Section: Hgrantx (Bus Grant)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Efficient Dual Mode Arbitration Scheme for Multiprocessor Hardware Interface in System-on-Chip

Motakabber,

Rokon,

Alam

et al. 2023

IJEEI

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“…In order to detail the methodology presented in Section III, we use a test case composed of 2 blocks: an I2C slave [23] connected to an AHB [16] bus master interface. Commands (read or write) along with parameters (address and data) are received on the serial line and transformed into a series of AHB read and write transactions.…”

Section: Test Casementioning

confidence: 99%

Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems

Fiorucci

Daveau

Natale

et al. 2021

2021 IEEE 27th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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In the field of automatic quality or safety assurance level evaluation, this paper proposes the first approach towards the automation of the extraction processes of both the valid and faulty state machines within a System-on-a-Chip. The data automatically extracted by this method is a relevant input for behavioural modelization and FMEA analysis. The method is based on a semi-automated approach for the systematic extraction of failure modes of a digital design in the hypothesis of a singleevent upset (SEU) or stuck-at in flip-flops. This procedure aims to enhance human driven failure analysis and provide inputs for RAMS frameworks in the process of quality assurance of complex devices. The main objective is to transport and apply RAMS methods and tools in the area of SoCs design. Experimental results have been conducted on an I2C -AHB system, laying the base for a complete and more complex analysis on an entire SoC.

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“…In the modern era, digital control is pervasive, extending from simple toys to sophisticated high-tech devices, all orchestrated by VLSI chips [1]. These chips have not only become increasingly complex to accommodate advanced functions but have also grown significantly in size.…”

Section: Introductionmentioning

confidence: 99%

Advancing System Integration: Verilog-Based Hardware Implementation of an Asic Interface for Three Amba Processors

Motakabber,

Rokon,

Alam

et al. 2024

IIUMEJ

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This paper presents the development of a multi-AMBA system processor interface employing multiple AMBA processors. The primary goal of this interface is to establish connections between various AMBA AHB interfaces and external memory units such as RAM and REGISTER, leveraging the high-performance capabilities of AMBA AHB. The research delves into the utilization of ASICs to integrate processors and functional blocks into a System-On-Chip (SoC) configuration, enabling the execution of intricate applications. Within the ASIC environment, the research explores how processors communicate with their designated targets through an interface that standardizes the communication protocol for all targets. It underscores the challenges posed by data throughput and inter-processor/RTL communication in contemporary processors and suggests the concurrent use of multiple AMBA processors for accessing their respective targets. Additionally, the paper introduces an arbitration system for managing multiprocessor access and investigates the optimization of bulk data access while prioritizing crucial ASIC design constraints, including speed, low power consumption, and efficient area utilization. The proposed system was rigorously validated through simulation using Verilog HDL, yielding positive and promising results. ABSTRAK: Kajian ini adalah mengenai pembangunan antara muka, sistem pemproses berbilang AMBA yang mengandungi berbilang pemproses AMBA. Tujuan antara muka ini adalah bagi mewujudkan hubungan pelbagai antara muka AMBA AHB dengan unit memori luaran seperti RAM dan REGISTER, ini sekaligus memanfaatkan keupayaan tinggi AMBA AHB. Kajian ini mengguna pakai ASIC bagi menyatukan pemproses dan blok berfungsi pada konfigurasi Sistem-Atas-Cip (SoC), membolehkan pelaksanaan aplikasi rumit. Pada persekitaran ASIC, kajian ini meneroka cara pemproses berkomunikasi dengan sasaran yang ditetapkan melalui perantaraan antara muka yang menyeragam protokol komunikasi bagi semua sasaran. Ia menggariskan cabaran yang ditimbulkan oleh pemprosesan data dan komunikasi antara pemproses/RTL dalam pemproses kontemporari dan mencadang penggunaan secara serentak pemproses berbilang AMBA bagi mengakses sasaran masing-masing. Selain itu, kertas kerja ini memperkenalkan sistem timbang tara bagi mengurus akses berbilang pemproses dan mengkaji akses data pukal yang optimum sambil mengutamakan kekangan reka bentuk ASIC, seperti kelajuan, penggunaan kuasa rendah dan penggunaan kawasan secara cekap. Sistem ini telah disahkan dengan teliti melalui simulasi menggunakan Verilog HDL, memberikan dapatan positif dan harapan baik.

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Design and Verification of AMBA AHB

Cited by 19 publications

References 2 publications

Efficient Dual Mode Arbitration Scheme for Multiprocessor Hardware Interface in System-on-Chip

Efficient Dual Mode Arbitration Scheme for Multiprocessor Hardware Interface in System-on-Chip

Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems

Advancing System Integration: Verilog-Based Hardware Implementation of an Asic Interface for Three Amba Processors

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