Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory

Abstract

An associative memory-based track finding approach has been proposed for a Level 1 tracking trigger to cope with increasing luminosities at the LHC. The associative memory uses a massively parallel architecture to tackle the intrinsically complex combinatorics of track finding algorithms, thus avoiding the typical power law dependence of execution time on occupancy and solving the pattern recognition in times roughly proportional to the number of hits. This is of crucial importance given the large occupancies typical of hadronic collisions. The design of an associative memory system capable of dealing with the complexity of HL-LHC collisions and with the short latency required by Level 1 triggering poses significant, as yet unsolved, technical challenges. For this reason, an aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project. The VIPRAM leverages emerging 3D vertical integration technology to build faster and denser Associative Memory devices. The first step is to implement in conventional VLSI the associative memory building blocks that can be used in 3D stacking; in other words, the building blocks are laid out as if it is a 3D design. In this paper, we report on the first successful implementation of a 2D VIPRAM demonstrator chip (protoVIPRAM00). The results show that these building blocks are ready for 3D stacking.

L1 track trigger for the CMS HL-LHC upgrade using AM chips and FPGAs

“…These boards were designed at FNAL for data delivery in high energy physics experiments. Two types of PRM have been developed: one with a full AM chip configuration and one with two Xilinx Ultrascale FPGAs and a socket which can accommodate VIPRAM [9] chips. Each Pulsar IIb board can accommodate two Pattern Recognition Mezzanine (PRM) boards; these boards perform the pattern recognition and track fitting.…”

“…The FNAL PRM board has a socket which can accommodate the soon-to-arrive VIPRAM [9] chip. One of the FPGAs is used to emulate the AM chip using synthesized HDL code, while the other FPGA is used to store the hits and to fit the matched patterns.…”

Associative Memory Pattern Matching for the L1 Track Trigger of CMS at the HL-LHC

“…The FNAL PRM board has two Xilinx Ultrascale FPGAs and a socket which can accommodate the next-to-come VIPRAM [5] chip. One of the FPGA is used to emulate the AM chip using synthesized HDL code, while the other FPGA is used to store the hits and to fit the matched patterns.…”

“…An ATCA shelf accommodates ten PulsarIIb boards and each of them can accommodate two PRMs. Two types of PRM have been developed: one with a full AM chip configuration and one with two Xilinx Ultascale FPGAs and a socket which can accommodate VIPRAM [5] chips.…”

Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

“…The target application for our CAM chip lies in high energy particle physics to filter data obtained from particle collisions in particle colliders. The filtering and detection of collision data needs to be done in real-time, and CAMs are the best hardware resource to do just this [3,6,[14][15][16][17][18].…”