Design and Test of a GBTX-Based Board for the Upgrade of the ALICE TOF Readout Electronics

Falchieri, D.; Antonioli, P.; Baldanza, C.; Giorgi, F. M.; Mati, Ayache; Tintori, C.

doi:10.1109/tns.2017.2707302

Cited by 2 publications

(2 citation statements)

References 9 publications

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“…The FPGA's GBTx connection consists of a single 40-bit large parallel lane of 80 MHz differential signals. The same configuration was previously tested on a GBTx test board developed before designing the DRM2, where a bit-error ratio lower than 10 −14 and a total jitter on the received clock around 50 ps had been measured [63]. As on the DRM1, an additional optical Slow Control Link (SCL) is implemented.…”

Section: Fpga (Microsemi Igloo2mentioning

confidence: 99%

ALICE upgrades during the LHC Long Shutdown 2

Acharya,

Acosta Hernandez,

Adamová

et al. 2024

J. Inst.

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A Large Ion Collider Experiment (ALICE) has been conceived and constructed as a heavy-ion experiment at the LHC. During LHC Runs 1 and 2, it has produced a wide range of physics results using all collision systems available at the LHC. In order to best exploit new physics opportunities opening up with the upgraded LHC and new detector technologies, the experiment has undergone a major upgrade during the LHC Long Shutdown 2 (2019–2022). This comprises the move to continuous readout, the complete overhaul of core detectors, as well as a new online event processing farm with a redesigned online-offline software framework. These improvements will allow to record Pb-Pb collisions at rates up to 50 kHz, while ensuring sensitivity for signals without a triggerable signature.

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Section: Fpga (Microsemi Igloo2mentioning

confidence: 99%

ALICE upgrades during the LHC Long Shutdown 2

Acharya,

Acosta Hernandez,

Adamová

et al. 2024

J. Inst.

View full text Add to dashboard Cite

show abstract

“…The FPGA -GBTx connection consists of a single 40-bit large parallel lane of 80 MHz differential signals. The same configuration was previously tested on a GBTx test board developed before designing the DRM2: we could measure a BER lower than 10 -14 and a total jitter on the received clock around 50 ps [6].…”

Section: Drmarchitecturementioning

confidence: 99%

DRM2: the Readout Board for the ALICE TOF Upgrade

Falchieri¹

2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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Abstract:For the upgrade of the ALICE TOF electronics, we have designed a new version of the readout board, named DRM2, a card able to read the data coming from the TDC Readout Module boards via VME. A Microsemi Igloo2 FPGA acts as the VME master and interfaces the GBTx link for transmitting data and receiving triggers and a low-jitter clock. Compared to the old board, the DRM2 is able to cope with faster trigger rates and provides a larger data bandwidth towards the DAQ. The results of the measurements on the received clock jitter and data transmission performances in a full crate are given. (CERN). Each of the 18 sectors is read out by four VME electronic crates, each hosting 9 or 10 TDC Readout Module (TRM) boards and one Data Readout Module (DRM) card. In order to cope with an increase of luminosity and of the interaction rate (up to 1 MHz in proton-proton collisions and 50 kHz in lead-lead collisions), we have designed a newer board, named Digital Readout Module 2 (DRM2). The card features a faster link towards the data acquisition system using the GBTx ASIC [2] and VTRx optical transceiver [3] from CERN, which allow to reach an user bandwidth towards the Data AcQuisition system (DAQ) of 3.2 Gb/s. The readout will be implemented with synchronous triggers at fixed bunch crossing values at 33 KHz, setting a matching window of 30 microseconds in the TDC ASIC installed in the TRMs, named the HPTDC. This solution will mimic a full-fledged continuous readout as all ALICE detector upgraded readout chains. The same link is also used for receiving triggers and a low-jitter clock, which is distributed to the front-end electronics. For the TOF detector the quality of this clock is crucial and a campaign of measurements on the clock received from the ALICE data acquisition card named CRU (Common Readout Unit) [4] has been carried out: we measured a RMS clock jitter as low as O(10) ps, which is compatible with the requirements.The paper presents the design details of the DRM2 board, together with the measurement results of the performances obtained working with DAQ cards (CRU and C-RORC), for what concerns the received clock quality and the data transmission bandwidth towards the DAQ.

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Design and Test of a GBTX-Based Board for the Upgrade of the ALICE TOF Readout Electronics

Cited by 2 publications

References 9 publications

ALICE upgrades during the LHC Long Shutdown 2

ALICE upgrades during the LHC Long Shutdown 2

DRM2: the Readout Board for the ALICE TOF Upgrade

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