Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study

Designing quantum-dot cellular automata counters with energy consumption analysis

“…The authors of [8] have made an early effort to implement QCA edge triggered flip-flops using innovative level converters. The same authors in [12] have designed n-bit synchronous counters based on JK flip-flops. In addition, another research has been fulfilled in [13] to present an optimized JK flip-flop for designing high speed counters.…”

“…As a result, any optimization in its complexity and performance directly improves the performance of whole system. To date, lots of studies have been carried out by the researchers in designing efficient QCA memory cells, such as different structures for random access memory cell [10,11,15], well-optimized QCA architectures for flip-flops [13][14][15][16][17][18] and counter designs [12,13]. In addition, logical and arithmetical circuit designs have been extensively investigated in several studies [20][21][22][23][24]28,29].…”

A novel idea of pseudo-code generator in quantum-dot cellular automata (QCA)

“…But to our knowledge, QCA flip-flop and sequential circuit designs have not been widely studied. In addition to R-S flip-flop a new method of falling edge-triggered flip-flop and counter study have been proposed by different authors [14] In the structures of D-latch that has been proposed in [7], the cell value is kept through a closed loop. This D-latch schematic structure is shown in Figure 6a.…”

Designing efficient QCA logical circuits with power dissipation analysis

“…One of the most accurate power dissipation models has been proposed by Timler and Lent [4] and an upper bound power dissipation for QCA circuits is estimated by Srivastava et al [6] based on it. Furthermore, in recent years, lots of investigations have been launched in order to design various digital circuits based on this technology; new designs for five-input majority gate [10][11][12][13]27,28], structures for one-bit full-adder cell [10,11,21,22], designs for flip-flops and memory cells [14,15,23], QCA complex gate designs [29,32] and also studies on reversible circuits [24,25] have been presented.…”