Design and simulation of CRC encoder and decoder using VHDL

Saleh, Adham Hadi; Saleh, Kamal Mohammed; Al-Azawi, Saad

doi:10.1109/isces.2018.8340557

Cited by 6 publications

(5 citation statements)

References 3 publications

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“…To identify and rectify bit errors that occur during data storage or transmission, the Hamming code network is used for error detection and correction. The hamming code generator encrypts message bits using extraneous bits [6]. Parity or redundant bits are positioned at various points in the message/input bits.…”

Section: Literature Reviewmentioning

confidence: 99%

“…to E6 are the same as inputs I3 to E6 whereas E0 to E2 are computed using Eqns. (5)(6)(7). The results obtained are tabulated in Tab.…”

Section: Fig 4 Block Diagram Of (7 4) Hamming Decoder Circuitmentioning

confidence: 99%

“…Hamming codes, also known as linear block codes, are a class of codes that, by combining parity and parity bits, conduct detection of error and error correction, resulting in efficient error detection and correction coding methods [6]. Redundancy bits are introduced to a Hamming communication network (HCN) for error detection and correction [1].…”

Section: Introductionmentioning

confidence: 99%

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Area and energy optimized Hamming encoder and decoder for nano-communication

Megha,

Premananda,

Kamat

2024

Journal of Electrical Engineering

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The Hamming code or Linear block code is used in communication to identify and repair errors. Redundancy bits are introduced to the Hamming communication network (HCN) for error detection and correction. It can detect two errors and correct one error. Quantum-dot Cellular Automata (QCA) is used for designing circuits with high switching speed and low energy dissipation. This work proposes a cost-effective QCA-based (7, 4) Hamming encoder and decoder design. Hamming encoder is designed using coplanar structure and the error detector used in Hamming decoder uses a multilayer structure. The effort is to optimize the area, cost, and energy dissipation. The work proposes a coplanar (7, 4) Hamming encoder and decoder. Hamming decoder is implemented in two parts a syndrome calculator and an error detector. Proposed (7, 4) Hamming encoder circuit reduces cell count by 49.47% compared to [1] and 9.52% compared to [12]. The proposed (7, 4) syndrome calculator has reduced cell count by 56.54%, an 11.11% reduction in total area compared to [1]. The proposed design reduces the cell area, QCA cost, and also energy dissipation. The designs are realized and QCA parameters are assessed in QCADesigner2.0.3 and energy is analyzed in QCADesigner-E.

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Section: Literature Reviewmentioning

confidence: 99%

“…to E6 are the same as inputs I3 to E6 whereas E0 to E2 are computed using Eqns. (5)(6)(7). The results obtained are tabulated in Tab.…”

Section: Fig 4 Block Diagram Of (7 4) Hamming Decoder Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Area and energy optimized Hamming encoder and decoder for nano-communication

Megha,

Premananda,

Kamat

2024

Journal of Electrical Engineering

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“…Saleh, dkk. [16] merancang dan melakukan simulasi CRC-8 encoder dan decoder menggunakan VHDL pada Xilinx FPGA. Novaldi, dkk.…”

Section: Pendahuluanunclassified

Perancangan dan Implementasi Encoder dan Decoder CRC-8 untuk Pendeteksian Error pada Transmisi Data antar Perangkat IoT

Priyadi

Wellem²

2022

mib

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Cyclic Redundancy Check (CRC) is a widely used error detection code in digital communication systems to detect errors in data transmitted between transmitter and receiver. With the development of Internet-of-Things (IoT) technology, where many devices communicate wirelessly, the application of error detection codes such as CRC is essential to obtain reliable communication. The computation of CRC can be implemented in hardware using a linear feedback shift register (LFSR) or in software with shift and bitwise exclusive OR (XOR) operations for polynomial division. Due to the frequent use of CRC in wireless communication for IoT, research for the design and implementation of CRC continues to this day. This study aims to design and implement the encoder and decoder of CRC-8 with generator polynomial 0x07 on IoT devices. Two algorithms for computing the CRC, namely bitwise computation using LFSR and another one using lookup tables, are implemented on the Arduino Uno R3 board. Two Arduino boards connected in serial were used to verify the encoder and decoder implementation in the data transmission and error detection process. The experiment results showed that the encoder could correctly calculate the CRC value from the input data. Furthermore, the computation using lookup tables takes about four times faster than the bitwise method but requires more memory. In contrast, the bitwise computation method requires less memory but slower computation time. When testing using input data of 128 characters, the bitwise-based encoder requires a computation time of 2.37 milliseconds, while the lookup table-based encoder utilizing a lookup table requires a computation time of 0.5 milliseconds. In the error detection test, the results demonstrated that the receiver could detect errors in the transmitted data with a percentage of 100%.

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“…Cyclic redundancy check (CRC) code is a highly error detection method which is integrity mechanism used in 5G industrial use, CRC codes can be consider as a first line of defense against errors by detection data packets corruption between the transmitter and receiver in a communication link [9]- [11]. CRC code is used for error detection for many applications like digital communication, control system, data storage and data compression [12].…”

Section: Introductionmentioning

confidence: 99%

Design of CRC circuit for 5G system using VHDL

et al. 2023

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In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

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Design and simulation of CRC encoder and decoder using VHDL

Cited by 6 publications

References 3 publications

Area and energy optimized Hamming encoder and decoder for nano-communication

Area and energy optimized Hamming encoder and decoder for nano-communication

Perancangan dan Implementasi Encoder dan Decoder CRC-8 untuk Pendeteksian Error pada Transmisi Data antar Perangkat IoT

Design of CRC circuit for 5G system using VHDL

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