Design and Simulation of Cascaded H-Bridge Multilevel Inverter With Statcom for Industrial Applications.

Abstract

This paper presents an investigation in power system for compensation of reactive power and harmonics of 13-level cascaded H-bridge (CHB) inverter. Due to their many advantages in terms of low power dissipation on power supplies, low harmonic contents, the topologies of multilevel inverters are being used in medium and high power applications such as an active power filter, FACTS devices and a machine current. To control the multilevel inverter, the selected switching techniques play an important role on elimination of harmonic distortion in generated output voltage. We can use "s" dc sources for 2s+1 level for calculating the number of levels. This model is used to calculate the instantaneous reactive power and design a control scheme using abc coordinates for reactive power compensation. The simulation result of MATLAB/Simulink software indicates the superior performance of the proposed control system as well as the precision of the proposed models.

ANN Fed High Gain Luo Converter based Reduced Switch Multilevel Inverter for Single Phase Network Bridged PV Arrangement

“…Generally the PV cell consists of semiconductor object. The terminal of PV device produce voltage and current to small loads likewise DC motors and lighting systems [2,13]. Mathematical layout of PV cell is designed using Mat lab.…”

“…Henceforth the environmental factors such as solar radiation and atmospheric temperature plays a vital role in power generation by PV modules [1]. Need for solar energy is rising approximately by 20-25% every year, during the past two decades [2].The potential for direct transformation of AC energy in affixing to reduced functioning cost and low emissions are the major merits. Hence the unimaginable penetration of PV systems in the power conversion system is understandable [3].…”

Design Analysis and Development of Inverter Topologies for Industries

“…The voltage difference between voltage V an and V ao is the voltage across the capacitor C 2 , which is V dc /2 as in Table 1. In Figure 2, a 3-Ф 7-level diode-clamped inverter is given and a common voltage DC bus is joint by each of the 3-Ф which is subdivided by 6 capacitors into 7-level [6]. The output possible voltage levels for each inverter phase with reference to zero i.e.…”

“…The output possible voltage levels for each inverter phase with reference to zero i.e. voltage V 0 is shown in table 2 [6]. When the switch of semiconductor device is ON, the state condition is one (1) and when the switch of semiconductor device is OFF, the state condition is zero (0).…”

“…For voltage level V dc /2, switches S 1 and S2 requisite to be turned ON; for voltage level -V dc /2, switches S 1 ' and S 2 ' requisite to be turned ON; and for voltage level 0, either pair (S 1 ,S 1' ) or (S 2 ,S 2' ) desires to be turned ON. Infigure 4, a 3-Ф 7-level capacitor-clamped inverter is given (similar of figure 2)[6].…”