Design and Simulation of Asymmetric Digital Subscriber Line (ADSL) Modem

Ibraheem, Omar W.; Khamiss, Nasser N.

doi:10.1109/ictta.2008.4530251

Cited by 8 publications

(6 citation statements)

References 3 publications

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“…To evaluate the proposed initialization method, an ADSL model that was tested in [6], will be established. The transceiver, BER and FEC calculation, the average SNR calculation are presented.…”

Section: Dsl Modemmentioning

confidence: 99%

A New Approach of Digital Subscriber Line2 Initialization Process

Khmiss¹,

Akrm²

2010

IJACT

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In this paper, a design for Asymmetric Digital Subscriber Line (ADSL)/Asymmetric Digital Subscriber Line2 (ADSL2) Initialization Process is presented which can be applied to different telephone network. Such a proposal can face the different types of noise over DSL channels, the most important types are Background and Crosstalk noises and Inter symbol interference (ISI) which is eliminated by using Time Domain Equalizer (TEQ). The Minimum Mean Square Error (MMSE) algorithm is implemented as TEQ algorithm. The initialization process where tested on American National Standard Institute (ANSI) defines 8 Carrier Serving Area (CSA) test loops for ADSL service. As a result, 9.02 Mbps and 9.42 Mbps were achieved over CSA loop-2 for ADSL and ADSL2 respectively. The TEQ efficiency for 8 CSA test loop are calculated where it achieved 93.1% of zero ISI for CSA power shows that NEXT have higher power and narrow band where NEXT powers were (-45.593) dBm for all loops and FEXT were ranging from (-76.353 to -68.261) dBm for the 8 loops. Finally the results show that ADSL2 outperforms ADSL by about 400Kbps which about 1.1%.

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Section: Dsl Modemmentioning

confidence: 99%

A New Approach of Digital Subscriber Line2 Initialization Process

Khmiss¹,

Akrm²

2010

IJACT

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“…In general, the input (time domain) and output (frequency domain) data of the FFT are complex and various pipelined complex-valued FFT architectures were proposed in the past [4]. However, in most modern applications such as bio-signal processing [5] or telecommunications [6], the inputs are real-valued, which urged many recent works to try to simplify the FFT architecture [7], [8], [9] by exploiting the conjugate symmetry of the output frequencies. The pipelined architectures [4], [7], [8], [9], process the data either in a serial or in a parallel manner [10], [11] and each one uses the same hardware elements; a butterfly unit, a rotator that is used for complex multiplication, and various memory elements.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Fast Fourier Transform for Real-Valued Applications

Eleftheriadis

Karakonstantis

2022

IEEE Trans. Circuits Syst. II

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This brief presents a new energy efficient Fast-Fourier Transform (FFT) architecture for real-valued applications. The proposed architecture decimates the FFT in time domain with bit-reversed inputs which allows to avoid the use of all costly complex FFTs operations required by the existing schemes. This leads to the reduction of the required memory by a factor of 2 while processing two inputs in parallel, thus doubling the throughput and improving the energy efficiency compared to the current real-valued FFT designs. Furthermore, the output frequencies are computed at their natural order by using a novel memory management technique, without requiring any reordering circuit unlike existing works. In summary for a N point FFT the proposed architecture leads to an increased throughput of 2 samples per clock cycle, requiring N − 2 memory cells, 8logN − 8 real adders and 3logN − 4 real multipliers. Our results show that we can achieve up to 46.86% energy savings when compared with recent real-valued FFT architectures.

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“…According to the input order of the data, the upper butterfly of the structure computes the pairs of samples (0, 8), (1,9), (2,10) and (3,11), whereas the lower butterfly operates samples (4, 12), (5, 13), (6,14) and (7,15).…”

Section: Comparison To Other Algorithms For the Computation Of Thementioning

confidence: 99%

“…Moreover, in implantable or portable devices [12], [13], a dedicated hardware can save power consumption. On the other hand, the RFFT is a key element in technologies based on DMT (discrete multitone) modulation, such as ADSL (Asymetric Digital Subscriber Line) or VDSL (Very high bit-rate Digital Subscriber Line) [14], [15]. Nowadays, high signal processing capabilities are required for second-generation standards (ADSL2/2+ [16] and VDSL2 [17]).…”

Section: Introductionmentioning

confidence: 99%

A Pipelined FFT Architecture for Real-Valued Signals

Garrido

Parhi

Grajal

2009

IEEE Trans. Circuits Syst. I

119

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Abstract-This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computation of the RFFT, which, contrary to previous approaches, presents a regular geometry suitable for the implementation of hardware structures. Moreover, the algorithm can be used for both the Decimation In Time (DIT) and Decimation In Frequency (DIF) decompositions of the RFFT and requires the lowest number of operations reported for radix 2.Finally, as in previous works, when calculating the RFFT the output samples are obtained in a different order. The problem of reordering these samples is solved in this paper and a pipelined circuit that performs this reordering is proposed.

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Design and Simulation of Asymmetric Digital Subscriber Line (ADSL) Modem

Cited by 8 publications

References 3 publications

A New Approach of Digital Subscriber Line2 Initialization Process

A New Approach of Digital Subscriber Line2 Initialization Process

Energy-Efficient Fast Fourier Transform for Real-Valued Applications

A Pipelined FFT Architecture for Real-Valued Signals

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