Design and simulation of a lumped element metal finger capacitor for RF-CMOS power splitters

Abstract

Design, development and simulation results of an interdigitated metal-fingers capacitors in 0.18f./,m RF-CMOS technology that are exploiting both lateral and vertical metal metal capacitances are presented. Two RF-CMOS capacitors are designed specifically for applications in a 2.45 GHz power splitter circuit. Five metal RF-CMOS layers are used to design two capacitors of 1.39pF and 2.2pF, consisting of 101 and 105 metal fingers respectively. The real impedance obtained at the input is Zl = 35.04r2 and Z2 = 39.73r2, while the insertion loss is 821 = 2.47dB. Return loss 811 and 822 are simulated as 4.042dB and 4.047dB respectively. Phase measurements of 110.9° and 101.20 are obtained for the input and output ports, indicating that the phase shift is not degraded too much due to the capacitor.

Role of MOSFETs Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode

“…The noise margins for two logic levels are expressed as: Relaying on fabrication processes advances of MOS transistors, it is possible that electrical and physical parameters which characterize MOS transistors can be controlled during fabrication process [1,3,6]. Therefore, we will examine the impact of these parameters on the particular magnitudes that characterize the CMOS inverter and based on them, can be defined the routes which lead to the design of the CMOS inverter with favorable performance according to the operation conditions and digital circuits based on CMOS logic [1,9,[15][16][17].…”

“…It's very important that the CMOS inverter has the static power of dissipation nearly zero, when the subthreshold conductions and leakage currents are neglected [7,[12][13][14][15]. …”