Design and sensitivity analysis of feed-forward neural ADC's

Movahedian, H.; Bakhtiar, Mehrdad Sharif

doi:10.1109/iscas.2004.1329933

Cited by 3 publications

(1 citation statement)

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“…Therefore, folding ADC needs an additional bit synchronization block [4]. In a folding analog-to-digital converter comparator and encoder are main parts and consume much of the total power [5] [6], so it is quite necessary to save comparators and simplify the logic design of the encoder to reduce power dissipation. In this paper, a special low-power CMOS folding and interpolating ADC is designed.…”

Section: Introductionmentioning

confidence: 99%

Low-power CMOS folding and interpolating ADC with a fully-folding technique

Liu

Wang

Jia

et al. 2007

2007 7th International Conference on ASIC

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A 8-bit 150MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-folding technique is designed in a 0.35µm standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one and in bit synchronization block to reduce the number of comparators for low power. A novel bit synchronization architecture based on folding circuits is presented. A low-power encoder using a novel arithmetic is adopted. The total power dissipation is merely 65mW at a 3.3V supply.

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Section: Introductionmentioning

confidence: 99%