10th IET International Conference on AC and DC Power Transmission (ACDC 2012) 2012
DOI: 10.1049/cp.2012.1985
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Design and PSPICE analysis of a grid connected multilevel converter with reduced number of switches

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Cited by 5 publications
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“…When these two converters are compared for switching losses and conduction losses under the same power rating, it can be realised from the gate signals given in [29] that four semiconductors (S1, S2, S5 and S6) in both converters are carrying the same amount of current and peak inverse voltages (PIV) during the SPWM switching. However, the PIV of two switches (S3 and S4) in proposed converter are two times higher than the others.…”
Section: Control Algorithmmentioning
confidence: 99%
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“…When these two converters are compared for switching losses and conduction losses under the same power rating, it can be realised from the gate signals given in [29] that four semiconductors (S1, S2, S5 and S6) in both converters are carrying the same amount of current and peak inverse voltages (PIV) during the SPWM switching. However, the PIV of two switches (S3 and S4) in proposed converter are two times higher than the others.…”
Section: Control Algorithmmentioning
confidence: 99%
“…2 b and c . Voltage spike is almost 1.2 times of the DC‐link voltage (sum of two capacitor voltages) [29] after connecting snubber circuit.…”
Section: Control Algorithmmentioning
confidence: 99%
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