Design and Power Dissipation Consideration of PFAL CMOS v/s Conventional CMOS based 2:1 Multiplexer and Full Adder

Abstract

Increasing transistor switching time and rising count of transistors integrated over a chip area has given a high pace in computing systems by several orders of magnitude. With the integration of circuits, number of gates and transistors are increasing per chip area. CMOS Logic family is preferred due to its performance and impeccable noise margins over other families. However with integration in every digital circuit, the energy due to switching of gate doesn’t decrease at same rate as gates are increased per chip area. Due to this, power dissipation becomes significant and also reduction of heat becomes more complicated and expensive. In CMOS based circuits dynamic power requirement is becoming major concern in digital circuits. In this paper, the work is focused on reducing the power dissipation in circuits which is increasing with down scaling of circuits. The work is done on 2:1 multiplexer and full adder circuit. Adiabatic logic with positive feedback (PFAL) is applied to redesign the circuit with input power taken as sinusoidal source of 3.3 V and analysis is done for power dissipation between conventional CMOS and PFAL based CMOS circuits. In comparison with the conventional CMOS 2:1 multiplexer circuit, the designed PFAL CMOS 2:1 multiplexer circuit has less power dissipation as 80.871 picoWatts while conventional CMOS circuit has 6.9090 nanoWatts with the same behavior of circuit. Also for full adder conventional CMOS circuit have 48.0452 picoWatts while PFAL based full adder has 3.9089 picoWatts.

Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties

“…In a study by Zean et al [3], they showed that CNTFETbased inverters showed a significant decrease in PDP as compared to silicon-based. This is further supported by research conducted by Aara et al [4] which highlighted the possible reduction in power consumption by 6.30% in a 2:1 MUX application using CNTFET. CNT material used in designing the Analog to Digital Converter (ADC) [5] also has been studied.…”

“…The outcome served as the guideline for researchers and experimentalists designing low-power circuits for future electronic device applications. Therefore, this paper simulates and characterizes the CNTFET-based 2:1 MUX application using the established SPICE model simulated in HSPICE extended those from reference [3], [4], and [7]. The electrical performance evaluated is the propagation delay, average power consumption, PDP, and EDP comparing design approaches which are conventional CMOS, PTL, and GDI approaches.…”