Design and performance of a prototype general purpose analog neural computer

Müeller, Paul; Spiegel, Jan Van der; Agami, V.; Aziz, P.M.; Blackman, David; Chance, P.; Choudhury, Anirban Dutta; Donham, C.; Etienne, R.; Jones, L. M.; Kinget, Peter R.; Koch, Werner; Kim, J.; Xin, Jianguo

doi:10.1109/ijcnn.1991.155223

Cited by 4 publications

(1 citation statement)

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“…The network has been configured for a number of applications, including a "winner take all" net, an associative network, a neural integrator, and several circuits for the computation of time-domain pattern primitives [27]- [29]. The latter ones have been realized by using feedback and synaptic time constants, which generate dynamic activity patterns in the absence of external inputs.…”

Section: (Dlgltal)mentioning

confidence: 99%

An analog neural computer with modular architecture for real-time dynamic computations

Spiegel

Müeller

Blackman

et al. 1992

IEEE J. Solid-State Circuits

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The paper describes a multichip analog parallel neural network whose architecture, neuron characteristics, synaptic connections, and time constants are modifiable. The system has several important features, such as time constants for time-domain computations, interchangeable chips allowing a modifiable gross architecture, and expandability to any arbitrary size. Such an approach allows the exploration of different network architectures for a wide range of applications, in particular dynamic real-world computations. Four different modules (neuron, synapse, time constant, and switch units) have been designed and fabricated in a 2µm CMOS technology. About 100 of these modules have been assembled in a fully functional prototype neural computer. An integrated software package for setting the network configuration and characteristics, and monitoring the neuron outputs has been developed as well. The performance of the individual modules as well as the overall system response for several applications have been tested successfully. Results of a network for real-time decomposition of acoustical patterns will be discussed. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Abstract-The paper describes a multichip analog parallel neural network whose architecture, neuron characteristics, synaptic connections, and time constants are modifiable. The system has several important features, such as time constants for time-domain computations, interchangeable chips allowing a modifiable gross architecture, and expandability to any arbitrary size. Such an approach allows the exploration of different network architectures for a wide range of applications, in particular dynamic real-world computations. Four different modules (neuron, synapse, time constant, and switch units) have been designed and fabricated in a 2-pm CMOS technology. About 100 of these modules have been assembled in a fully functional prototype neural computer. An integrated software package for setting the network configuration and characteristics, and monitoring the neuron outputs has been developed as well. The performance of the individual modules as well as the overall system response for several applications have been tested successfully. Results of a network for real-time decomposition of acoustical patterns will be discussed. Author(s)Jan

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Section: (Dlgltal)mentioning

confidence: 99%