Design and optimization of double-resurf high-voltage lateral devices for a manufacturable process

Imam, Mohamed A.; Hossain, Z.; Quddus, Mohammed Tanvir; Adams, Jeff C.; Hoggatt, Charles; Ishiguro, Takeshi; Nair, R.S.

doi:10.1109/ted.2003.814981

Cited by 64 publications

(18 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to demonstrate the performance functionality of the proposed structure, a test chip containing a set of NMOS devices with different body P + contact structures (floating, CMOS conventional BTS, and proposed BTS) along with several CMOS and LDMOS devices is designed. The technology is based on a fully manufacturable bulk CMOS process targeting power conversion markets [15] with a high resistivity P-type float-zone wafer substrate, on which an N-well implant is performed with a subsequent drive. To form the body region of the tested NMOS devices, a P-tub implant and a subsequent drive are performed.…”

Section: Resultsmentioning

confidence: 99%

An area efficient body contact for low and high voltage SOI MOSFET devices

Daghighi

Osman

Imam

2008

Solid-State Electronics

View full text Add to dashboard Cite

Section: Resultsmentioning

confidence: 99%

An area efficient body contact for low and high voltage SOI MOSFET devices

Daghighi

Osman

Imam

2008

Solid-State Electronics

View full text Add to dashboard Cite

“…One configuration of a double-RESURF structure is illustrated in Fig. 7.14 [13,14]. The noticeable change from the single RESURF case is the addition of the P top region.…”

Section: Reduced Surface Field Resurfmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

View full text Add to dashboard Cite

This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

show abstract

“…4 illustrates that the proposed device can produce an inversion layer at the buried-oxide/p-sub interface under high V ds condition. The high concentration negative space charges in the inversion layer, just like a depleted high doping concentration buried-pwell, bring about better RESURF effect [5]. Meanwhile, the buried-oxide may enhance the vertical breakdown voltage for its small dielectric constant and high critical electric field [6].…”

Section: Device Performances Simulationsmentioning

confidence: 99%

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

Zhang

Liu

Sun

et al. 2014

IEICE Electron. Express

View full text Add to dashboard Cite

A novel lateral double diffused MOSFET (LDMOS) structure with partial buried-oxide layer under the n-drift region, which is suitable for the bulk silicon epitaxial process, is proposed. The introduction of the buried-oxide layer produces an inversion layer at buried-oxide/p-sub interface and achieves better reduced surface field (RESURF) effect comparing with the conventional device with buried-pwell. Moreover, the buried-oxide can prevent the impurity diffusion and improve the doping concentration of the ndrift region. As a result, the proposed structure improves the breakdown voltage about 12% and increases the current capability over 30% at the same time.

show abstract

Design and optimization of double-resurf high-voltage lateral devices for a manufacturable process

Cited by 64 publications

References 4 publications

An area efficient body contact for low and high voltage SOI MOSFET devices

An area efficient body contact for low and high voltage SOI MOSFET devices

High-Voltage and Power Transistors

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

Contact Info

Product

Resources

About