Design and optimization of collection efficiency and conversion gain of buried p-well SOI pixel X-ray detector

Abstract

Buried P-Well (BPW) technology was used in silicon-on-insulator pixels (SOIPIX) to suppress the back-gate effect, the major challenge in SOIPIX. In this work, we have designed and optimized two novel pixel structures, which are based on different BPW design layouts, to study the carrier collection efficiency and conversion gain of the pixel unit used in SOIPIX X-ray detectors. The first structure has an extended BPW region connected with a P+ node. In the second structure, a separated BPW ring region is formed surrounding the P+ node. Two X-ray sources with different photon energies have been applied in the simulation of excess carrier generation. The results indicated that the first structure had higher collection efficiency while the second structure had a slightly better conversion gain. As a result, the total photoelectric voltage of the first structure is about two times that of the second structure, where low doping concentration (<1 × 10 16 cm -3 ) in the BPW region is preferred. Such a study of design and optimization of BPW technology is very important for applications in SOIPIX detectors.