Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters

High-Frequency Oscillator Design for Integrated Transceivers

“…The generated jitter can be calculated by applying (4.11), using the integration limits specified in Table 4.3. Integration of the area under the total PLL noise over the frequency range fL to fH, and normalization to one period calculates to a jitter of 4.7 mUlnns [243]. Therefore, the jitter generation specification for SONET OC-3 is met by this PLL design (see Table 4.3).…”

“…The output spectrum of a SONET OC-3 clock-conversion PLL is shown, which includes a VCO running at 622 MHz [243] .…”

“…Note that an IC technology usually has one fMAX figure specified, which usually is valid for the best transistor under peak fr current, the error of oscillation frequency estimator (6.22) with respect to the simulation results using the MEXTRAM model is less than 12%. Figure 6.14 shows the circuit diagram of a VII-converter, which was designed for a 622 MHz version of the oscillator in Figure 6.12 [243]. The oscillator with V /I-converter is part of a clock-conversion PLL for SONET OC-12 (SDH STM-4) optical transmitters, and implemented in an 18 GHz fr BiCMOS technology.…”

“…The LO is part of the wide-band loop and controlled by the output voltage of a loop-~lter. It needs to have a high-ohmic voltage tuning-input, otherwise leakag~ .of charge in th.e loop filter would result in reference-breakthrough signals [243]. I~ add1t1on, the bandw.1dth of the tuning input circuitry must be sufficiently high (e.g.…”