Design and Optimization of A 4-bit Absolute-value Detector Using Half Adder and Comparator

Abstract

In this paper, a design and optimization of a 4-bit absolute value detector is realized by using the CMOS technique, transmission gates, and the traditional comparator, which can compare the two positive input values all expressed in binary form. To optimize the overall performance of the absolute value detector, this paper chooses to minimize the number of transistors and simplifies the circuit through logical analysis. As for calculating the overall delay and energy consumption, critical path identification is also studied and analyzed in this paper. Based on the theory of path effort and path parasitic delay, the grid capacitance and resistance are introduced into the calculation of inverter ratios. To achieve various optimization objectives, this study also combines the grid size and power supply voltage scaling techniques to reduce the delay and energy of the circuit, and finally finds the minimum energy loss at a 1.5x delay. The overall delay and energy can be expressed by the multiple of the unit size inverter of that. As a compromise, a minimum delay of 1.5 times is selected to reduce energy consumption by 39.16 %.

A methodology of designing and optimising a 4-bit absolute-value detector for the application of Brain-computer Interface

“…Huang focused on using CMOS for logic gate design [6]. Carlson, Dewdney et al selected a half-adder in the transcoder module and combined CMOS and pass-transistor logic (PTL) to reduce the number of transistors [7]. Jia designed a combinational logic circuit for transcoding and applied full adders to the comparator module [8].…”

Design of 4-bit absolute value detector with low energy

“…The overall power consumption can be reduced while maintaining performance and accuracy by improving transistor size. Layout optimization is done to lower parasitic capacitances and resistances and improve overall circuit performance [13].…”

“…Pass-transistor approximate adders are a form of circuit design that forgoes complete accuracy in favor of increased efficiency and lower power consumption. These adders operate by combining digital and analog components to carry out calculations swiftly and accurately [13]. When used in real-world applications like digital signal processing or machine learning algorithms, these adders can significantly enhance performance and energy efficiency without compromising accuracy.…”

The performance optimization of 4-bit absolute-value detector

“…To optimize the circuit's performance, she avoided using high fan-in gates in the circuit topology to minimize the parasitic delay, made a shorter critical path to minimize the critical-path delay, and replaced traditional comparators with chain adders to reduce the number of transistors used. Yao put forward a circuit structure that uses truth table to build the comparator and uses half adders and transmission gates to get the absolute value of the input signal [6]. In order to optimize the performance of the circuit, he used pass transistor logic gates instead of traditional static CMOS logic gates.…”