Design and Optimization of a Low-Power Comparator for a 10-Bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for General-Purpose Applications

M P, Tejas; Venkateshappa,

doi:10.1109/iitcee59897.2024.10468012

2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE) 2024

DOI: 10.1109/iitcee59897.2024.10468012

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Design and Optimization of a Low-Power Comparator for a 10-Bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for General-Purpose Applications

Tejas M P,

Venkateshappa

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Design and Optimization of a Low-Power Comparator for a 10-Bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for General-Purpose Applications

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