Design and migration challenges for an Alpha microprocessor in a 0.18 μm copper process

Hokinson, R.; Benschneider, B.J.; Arneborn, M.; Clay, Dempsey; Clouser, J.; Dumford, S.; Kalathur, V.; Kalidindi, V.; Kovvali, S.; Krause, J; Maresh, S.; Munger, Benjamin; O'Neill, N.; Pragaspathy, I.; Qin, Wei; Sasamori, R.; Sayadi, Sami; Singh, T.; Tang, John; Tracz, M.; Watkins, Simon P.

doi:10.1109/isscc.2001.912656

Cited by 1 publication

(3 citation statements)

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“…Thus (3) Function is also monotonically decreasing; thus, from (2) and (3) and from the proportionality of with for all clock domains , i.e., we get which shows that the synchronous pipeline performs better energy-wise than the GALS version for the same slowdown factor (or performance penalty) under the assumptions of Lemma 1. This result is in fact a generalization of the optimal voltage-scheduling problem for applications with hard real-time constraints.…”

Section: Choice Of Dynamic Control Strategymentioning

confidence: 67%

“…In [2], the designers of the Alpha 21264 microprocessor present the problems encountered when migrating the design to a 180-nm copper process and how the nonscalability of wire delays is affecting this migration process.…”

Section: Motivationmentioning

confidence: 99%

“…As recent case studies show [2], [3], the circuitry needed for driving such frequencies is already a dominant source for power consumption. Adding more and more transistors on a single die tends to worsen the problem-larger clock nets require more and more power.…”

Section: Introductionmentioning

confidence: 99%

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Toward a multiple clock/voltage island design style for power-aware processors

Talpes

Marculescu

2005

IEEE Trans. VLSI Syst.

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Abstract-Enabled by the continuous advancement in fabrication technology, present-day synchronous microprocessors include more than 100 million transistors and have clock speeds well in excess of the 1-GHz mark. Distributing a low-skew clock signal in this frequency range to all areas of a large chip is a task of growing complexity. As a solution to this problem, designers have recently suggested the use of frequency islands that are locally clocked and externally communicate with each other using mixed clock communication schemes. Such a design style fits nicely with the recently proposed concept of voltage islands that, in addition, can potentially enable fine-grain dynamic power management by simultaneous voltage and frequency scaling. This paper proposes a design exploration framework for application-adaptive multiple-clock processors which provides the means for analyzing and identifying the right interdomain communication scheme and the proper granularity for the choice of voltage/frequency islands in case of superscalar, out-of-order processors. In addition, the presented design exploration framework allows for comparative analysis of newly proposed or already published application-driven dynamic power management strategies. Such a design exploration framework and accompanying results can help designers and computer architects in choosing the right design strategy for achieving better power-performance tradeoffs in multiple-clock high-end processors.

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Section: Choice Of Dynamic Control Strategymentioning

confidence: 67%

Section: Motivationmentioning

confidence: 99%