Design and measurement of 450MHz LNA utilizing 0.13um RF CMOS process

Salleh, Syahrizal; Hashim, Mohamad Faizal; Rahman, Abdul Aziz Abdul; Majid, Zulkepli

doi:10.1109/iswta.2012.6373876

Cited by 2 publications

(2 citation statements)

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“…1. In that technique, the LC network modify the series resistance of gate inductor to 50-Ω [4]. Moreover, by eliminating the source inductor, the bandwidth of the LNA can be significantly reduced compared to the other implementation [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Noise modeling of source inductive degeneration low noise amplifier in 0.18-µm CMOS technology

Kurniawan

Wibisono

2013

2013 IEEE International Conference on Communication, Networks and Satellite (COMNETSAT)

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This paper presents a mathematical modeling of noise performance in source inductive degeneration topology which widely used in narrow band amplifier. The proposed model is conducted by utilizing a small-signal MOSFET model to generate the effective transconductance of circuits. The performance of noise figure can be preserved by selecting the device width while preserving a stable bias voltages and maintaining the device length unchanged. Using the mathematical model, a low noise amplifier is designed and obtain the noise figure of 2.5-dB, an remarkable figure of merit among reported LNAs in 0.18-µm CMOS technology.

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Section: Introductionmentioning

confidence: 99%

Noise modeling of source inductive degeneration low noise amplifier in 0.18-µm CMOS technology

Kurniawan

Wibisono

2013

2013 IEEE International Conference on Communication, Networks and Satellite (COMNETSAT)

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“…At present in the interface formation, silicon and III-V compounds (such as GaAs) maybe acted as the base material in high frequency applications [1][2][3]. In order to determine the D it value of these devices, it usually uses the Terman method [4][5][6][7][8][9] initially, and the quality of interface structure within oxide can be known that by D it .…”

Section: Introductionmentioning

confidence: 99%

Lateral Non-Uniformity Charges Influence on Interface Trap Density (D<sub>it</sub>) by Terman Method in the nMOS Fabrication

Chen

Chang

2013

AMR

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Generally speaking, the oxide interface quality can be determined by the interface trap density (Dit) distribution. In this paper, the Dit quantity obtained from the Terman method, which it is assumed that the Dit is equal to zero at the beginning for simulating the Dit effect in ultra-thin oxide. However, the lateral non-uniformity charges have existed in the oxide layer, which maybe obtained an equivalent Dit density not equal to zero also producing an equivalent Dit value. And, such faked Dit will be resulted in an error in high frequency measurement. Fortunately, it can be solved by differentiating technique to obtain an accuracy Dit quantity.

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Design and measurement of 450MHz LNA utilizing 0.13um RF CMOS process

Cited by 2 publications

References 10 publications

Noise modeling of source inductive degeneration low noise amplifier in 0.18-µm CMOS technology

Noise modeling of source inductive degeneration low noise amplifier in 0.18-µm CMOS technology

Lateral Non-Uniformity Charges Influence on Interface Trap Density (D<sub>it</sub>) by Terman Method in the nMOS Fabrication

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Design and measurement of 450MHz LNA utilizing 0.13um RF CMOS process

Cited by 2 publications

References 10 publications

Noise modeling of source inductive degeneration low noise amplifier in 0.18-&#x00B5;m CMOS technology

Noise modeling of source inductive degeneration low noise amplifier in 0.18-&#x00B5;m CMOS technology

Lateral Non-Uniformity Charges Influence on Interface Trap Density (D<sub>it</sub>) by Terman Method in the nMOS Fabrication

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Noise modeling of source inductive degeneration low noise amplifier in 0.18-µm CMOS technology

Noise modeling of source inductive degeneration low noise amplifier in 0.18-µm CMOS technology