Design and Investigative Aspects of RF-Low Power 0.18-µm based CMOS Differential Ring Oscillator

Raman, Ashish; Sarin, R. K.

doi:10.14257/ijast.2013.58.08

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Comparison Study Of Each Topology1

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“…[22] 2013 [37] 2013 [36]. [41] 2012 [39] 2012 [4] 2011 [26] 2011 [25] 2009 [42] 2012 [35] Technology (nm) 180 180 180 180 350 180 180 180 130 90 Number of Stages 5 5 3 3 3 4 3…”

Section: Comparison Study Of Each Topologymentioning

confidence: 99%

CMOS ring oscillator delay cell performance: a comparative study

Hadi¹,

Jidin²,

Wahab³

et al. 2019

IJECE

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A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.

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“…[22] 2013 [37] 2013 [36]. [41] 2012 [39] 2012 [4] 2011 [26] 2011 [25] 2009 [42] 2012 [35] Technology (nm) 180 180 180 180 350 180 180 180 130 90 Number of Stages 5 5 3 3 3 4 3…”

Section: Comparison Study Of Each Topologymentioning

confidence: 99%