Design and Investigation of Gate Stacked Vertical TFET with N+ SiGe Pocket Doped Heterojunction for Performance Enhancement

Abstract

In this paper, a novel delta-doped N + Silicon-Germanium Gate Stacked Triple Metal Gate Vertical TFET (Delta doped N + GS TMG VTFET) is proposed and investigated using the Silvaco TCAD simulation tool. Four different combinations were presented and compared with and without the gate stacking method and Si0.2Ge0.8 N + pocket delta-doped layer to render the optimized results. Among all, Delta doped N + GS TMG VTFET structure comes out with a very steep sub-threshold slope (9.75 mV/dec), 40 % lower than the first configuration of TMG VTFET. The inclusion of the N + delta-doped layer between the source and channel and gate will enhance the ON-state drive current performance by reducing the OFF-state leakage current. This happens due to the lower bandgap of the N + delta-doped layer cause narrow BTBT, which results in a high drive current. The Triple metal gate is designed to mitigate the ambipolar conduction by modulating the optimized wok function at 4.15, 4.3, and 4.15 eV. The distribution of the source channel in the vertical structure will enhance the device's scalability due to the electron tunneling moves in the vertical electric field direction. The optimally constructed structure demonstrates improved performance, such as a high ION/IOFF current ratio (~ 1013) and sub-threshold voltage (0.33 V). The results obtained from the proposed device make it suitable for the ultra-low-power device application.