Design and Implementation of Scan Flip-flop for Processor Using QCA Technology

Abstract

The present day technology is more improved. Many devices like processors, digital circuits, controllers etc. can be designed with good performance like high speed operation, less power consumption and reduction in sizes. In this paper a scan flip-flop is designed using 2:1 Mux and D flip-flop. A scan flip-flop is being used in processors for built in self-test. They can scan the internal chip and detect their fault before fabrication. So this helps to reduce time and cost. At the time of testing after fabrication if any fault is detected, it leads to waste of money and effort of our work. Quantum Cellular Automata is a encouraging nanotechnology that has accepted as one of the top six incipient technology in imminent computers. We have urbanized a new methodology in QCA design of 2:1 MUX, D flip-flop and a Scan flip-flop using efficient MUX and D flip-flop. These circuits designed by QCA, evidenced to have better area proficiency and less input to output delay compared to CMOS design. QCA Designer simulator tool is used to test the proposed design. The tools used to simulate the circuits are QCA designer tool and Cadence tool. Cell count of the proposed design is very less compared to previous design. Thus there is reduction in area usage. Also the power dissipation is 0.079X10 -15 J, which is very less. The area occupied by QCA designed scan flip-flop are in nm^2 whereas CMOS designed scan flip-flop occupied area in µm.

Flip Flops Design in Quantum Dot Cellular Automata Technology: Towards Digitization

“…The output of the and CMOS technology. According to Shanthala G M et al [16], the researcher can design more complicated circuits using this technique.…”