Design and Implementation of Router for NOC on FPGA

Verma, Gaurav; Agarwal, Harsh; Shreya, Singh; Khanam, Shaheem Nighat; Gupta, Prateek K.; Jain, Vishal

doi:10.14257/ijfgcn.2016.9.12.24

Cited by 5 publications

(2 citation statements)

References 6 publications

(6 reference statements)

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“…The chip design was focused on mesh and ring topological network modeling, simulation, and synthesis. The cluster size was regarded as (2×2), (4×4), (8×8), (16×16), (32×32), (64×64), (128×128), and (256×256) for 2D NoC router design [12]. The projected design decreased the 227 quantities of data frames navigated for long-distance communication, according to simulation results.…”

Section: Related Workmentioning

confidence: 99%

2D router chip design, analysis, and simulation for effective communication

Agarwal

Garg

Kumar

2023

IJ-ICT

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<p class="Correspondencedetails"><span lang="EN-US">The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.</span></p>

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Section: Related Workmentioning

confidence: 99%

2D router chip design, analysis, and simulation for effective communication

Agarwal

Garg

Kumar

2023

IJ-ICT

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“…NoC is an integrated network that uses routers to allow the communication among those blocks. It uses networking theory methods for on chip communications where the blocks exchange information on a chip [5].…”

Section: Introductionmentioning

confidence: 99%

Design of Priority Based Reconfigurable Router in Network on Chip

2020

Informacije MIDEM

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Network on Chip (NoC) is an advanced integration design for communication networks while providing a solution to the traditional bus based System on Chip designs (SoC) too. A router is a key component which is considered as the backbone of communication in NoC. The objective of this work is to design a priority based reconfigurable router for NoC. Initially, a 4x4 Baseline router is designed and synthesised and then the channels inside the router are modified to achieve reconfiguration to improve the router's efficiency. In 4x4 Reconfigurable Router the slots are well utilized but prioritization portion is not considered. Routers are associated with switches to take data transfer decisions resulting in high power consumption. In order to overcome this problem, a new priority based reconfigurable router is designed. The design for this router is carried out using Verilog HDL and synthesized and simulated using Xilinx ISE Design Suite 14.3 and ModelSim-Altera 6.5b Software respectively. The corresponding results in terms of power, energy efficiency, area and delay are analysed and the proposed work gives better results than the conventional Baseline Router. Dizajn prioritetno nastavljivega usmerjevalnika v omrežju na čipuIzvleček: Omrežkje na čipu (NoC) je napredna integracija komunikacijskih omrežij z uporabo tradicionalnih sitemov na čipu na osnovi vodil (SoC). Usmerjevalnik predstavlja ključno komponento v komunikaciji preko NoC. Namen dela je razvoj prioritetno nastavljivega usmerjevalnika za NoC. V osnovi je uporabljen 4x4 usmerjevalnik, v kateremu so, za doseganje učinkovitosti, kanali naknadno razširjeni.Reže v nastavljivem usmerjevalniku so dobro uporabljene, vendar ne upoštevajo prioritet. Usmerjevalniki so povezani s stikali za prenos podatkov, ki imajo visoko porabo. Nastavljivi usmrjevalniku rešujejo problem visoke porabe. Dizajn usmerjevalnika je realiziran v Verilog HDL okolju in simuliran z Xilinx ISE Design Suite 14.3 in ModelSim-Altera 5.5b programsko opremo. Rezultati izkazujejo boljšo učinkovitost, nižjo porabo in zakasnitev predlaganega usmerjevalnika.

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