Design and implementation of proposed 320 bit RC6-cascaded encryption/decryption cores on altera FPGA

Abstract

This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.

Development and evaluation of a 2oo3 safety controller in FPGA using fault tree analysis and Markov models

“…In this system, three pressure sensors operate in parallel and are responsible for measuring and transmitting any deviation of the pressure parameter towards a dangerous state. The logic processing system is based on FPGA technology with 2oo3 architecture in [23]- [28]. Its role is to collect the signals from the sensors, process them, and control the associated actuator.…”

“…In this case, using the reliability equations in [21], [22], new equations are proposed for redundant architectures. In [23]- [25], the authors present the parallel processing capabilities of FPGA to efficiently implement multiple tasks to be executed simultaneously, which can significantly reduce the system execution time. In [26]- [28], the authors present the design and implementation of the 1oo4 redundant architecture in FPGA.…”

FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review

“…The proposed encryption system's findings and its security review show that the encryption solution studied will protect high speed and safety against numerous attacks. Zong, Jianyou, et al, [52] Hashim, Ashwaq, et al, [53] Tried to develop the cryptographic algorithm simple, powerful and stable. The consequence of this effort is the 320-bit RC6-Cascade, the same as the cipher block.…”

An efficient controller-based architecture for AES algorithm using FPGA

“…The findings acquired are carefully contrasted with the outcomes of a traditional implementation in order to provide light on the efficacy and efficiency of the suggested improvements. Some of FPGA-based cryptography schemes [17]- [19] are subject to the following restrictions: i) limitations on resources: the amount of logic elements on FPGAs is limited, thus implementing AES can need a lot of resources. More resources might be needed for bigger key sizes and more complex encryption schemes.…”