Design and implementation of PN sequence generator using Vedic multiplication

Abstract

In wide communication network, signals are transferred and receive. In case of wireless systems transferring a signal over a wide spectrum and providing a security to such signal is a tough task. While transferring a signal extra security is needed to hide the original message signal, to provide such security Pseudo Noise sequence is used. PN sequence uses linear feedback shift register (LFSR). A Vedic multiplier is an ancient method of mathematics using Vedic sutras. Uradhava triyakabham (vertically and crosswise) is one of the sutra used for design of fast and efficient multiplication. VHDL simulation of Vedic multiplier is done.