Design and Implementation of Optimized FIR Filter using CSA and Booth Multiplier for High Speed Signal Processing

Sravani, K.; Saisri, M.; Sivani, U. Vidya; Kumar, A. Ramesh

doi:10.1109/incet57972.2023.10170547

Cited by 2 publications

(1 citation statement)

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“…Addition, subtraction, and multiplication are fundamental arithmetic operations in digital signal processing (DSP) applications, such as convolution [1,2], finite impulse response (FIR) [3,4], and Fast Fourier transform (FFT) [5,6]. The multiplier is the most complex, time-consuming, and energy-hungry component.…”

Section: Introductionmentioning

confidence: 99%

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Yu,

Pan,

Tang

et al. 2024

Electronics

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The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.

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