Design and Implementation of NFC Smart Card SoC with eSTT-MRAM IP

Lu, Kaiwen; Liu, Xingjie; Chen, Yong; Li, Dongsheng; Liu, Bo; Wu, Liang

doi:10.1109/icsict49897.2020.9278138

Cited by 1 publication

(1 citation statement)

References 5 publications

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“…Finally, we use the 180 nm CMOS process to make the fully integrated SoC reader we designed into a chip and its chip layout is shown in the Figure 6 below, which is a highly integrated chip that integrates RF analog circuit, single-chip microcomputer, protocol processing logic and memory, with an area of 2617

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m. Table 2 summarizes the parameters of the SoC and compares them with other similar works, reference [ 23 ] synthesizes UHF and HF communication protocols, literature [ 24 , 25 ] and this paper work is similar are designing a multi-standard highly integrated HF RFID reader SoC, compared to this paper’s area is more advantageous, literature [ 26 ] designs a single standard HF RFID reader SoC, this paper is compatible with more protocols in the case of a slightly smaller area From the table, it can be seen that the proposed reader SoC has the advantages of high integration and small area.…”

Section: Measurement Results and Analysismentioning

confidence: 99%

A Fully Integrated RFID Reader SoC

Hu,

Mei,

et al. 2023

Micromachines

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The traditional RFID reader module relies on a discrete original design. This design integrates a microcontroller, high-frequency RFID reader IC and other multiple chips onto a PCB board, leading to bottlenecks in cost, power consumption, stability and reliability. To align with the trend towards high integration, miniaturization and low power consumption in RFID reader, this paper introduces a fully integrated RFID Reader SoC. The SoC employs the open-source Cortex-M0 core to integrate the RF transceiver, analog circuits, baseband protocol processing, memory and interface circuits into one chip. It’s compatible with ISO/IEC 14443 A-type and B-type and ISO/IEC 15693 transmission protocols and rates. Manufactured using a 0.18 μm process, the chip is compatible with multiple standards. The optimized design of the digital baseband control circuit results in a chip area of only 11.95 mm2 offering clear advantages in both area and integration compared to similar work.

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Section: Measurement Results and Analysismentioning

confidence: 99%