Design and Implementation of Memory BIST for Hybrid Cache Architecture

Ghale, Suraj B; Namita, P

doi:10.1109/icces51350.2021.9489225

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Mbist Architectures For Diagnosis1

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2024

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“…The introduction of Memory Built-In Self-Test (MBIST) modules led to a test time reduction for which the magnitude depends on the MBIST structure and the CPU's and firmware's ability to access the memory [12][13][14]. Consisting of specialized hardware surrounding the memory, MBIST enables at-speed self-testing without the need for expensive and high-frequency Automated Test Equipment (ATE).…”

Section: Mbist Architectures For Diagnosismentioning

confidence: 99%

Built-In Self-Test Architecture Enabling Diagnosis for Massive Embedded Memory Banks in Large SoCs

Bernardi,

Guerriero,

Insinga

et al. 2024

Electronics

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This paper describes a hardware/software strategy for the effective and efficient management of several distributed Memory Built-In Self-Test (MBIST) units orchestrated by a single CPU to enable the parallel testing of several memory banks. Experimental testing of the implementation on an Infineon chip shows up to a 25% test time reduction compared to traditional strategies, especially in cases for which there are a large number of failures affecting several banks. Additionally, it permits balanced failure collection from different banks in cases for which there are limitations to the storage of failure-related information.

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Section: Mbist Architectures For Diagnosismentioning

confidence: 99%