Design and Implementation of Local Threshold Segmentation Based on FPGA

Abstract

In the process of the development of image processing technology, image segmentation is a very important image processing technology in the field of machine vision, pedestrian detection, medical imaging, and so on. However, the traditional image segmentation technology cannot solve the problems of reflection and uneven illumination. This paper presents a local threshold segmentation method based on FPGA, which can automatically select the optimal threshold according to different gray levels of images. First, the image is processed by mean filtering to remove noise interference in the image. Then, the idea of the mean value of the local neighborhood block and the Gaussian weighted sum in the local neighborhood is used to deal with the reflective and uneven light on the image. The process is designed and realized on FPGA. Finally, the design algorithm is verified by ModelSim simulation software and QT5 software. The experimental results show that the algorithm can effectively solve the problems of reflection and uneven illumination on the image surface, and the segmentation effect is significantly improved compared with the fixed threshold algorithm and Otsu algorithm. It also has certain reference value in medicine, agriculture, engineering, and other fields.

A Survey of Diverse Segmentation Methods in Image Processing

“…The local thresholding based on FGPA proposed to solve the uneven illumination and reflection problem by adopting the mean value of neighbourhood blocks and Gaussian weighted sum design idea in the local neighbourhood [7]. An algorithm for more precise and faster segmentation of the target curve, known as quasi-bimodal threshold segmentation (QBTS), which converts the multimodal histogram into a quasi-bimodal histogram proposed by Ruan et al [8].…”

Optimizing FPGA-Based Target Detection: A Hybrid Winograd-GEMM Accelerator with Enhanced Resource Efficiency and Throughput

“…As the number of parameters in the operation of the network model of CNN continues to grow, convolutional neural networks (CNNs) can be accelerated by using GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), and FPGA-based architectures. However, the CPU (Central Processing Unit) is no longer suitable for large-scale parallel computing, and GPUs are not suitable for use in low-cost embedded systems due to their high cost and power consumption [8]. ASICs have lengthy design cycles and minimal reconfigurability [9].FPGAs are more reconfigurable than ASICs, consume less power than GPUs, and are simpler to deploy, and can be adjusted to handle various scenarios.…”