Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)

Chen, Shin-Kai; Li, Youfu; Wu, Tsung-Yi; Tsai, Alexander C.

doi:10.1109/tcsi.2013.2248851

Cited by 16 publications

(6 citation statements)

References 31 publications

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“…Chen et al 2013 designed and implemented an energy-efficient variable-latency speculating Booth multiplier (VLSBM) to increase the functionality in a gloomy process [19]. To reduce complexity the VLSBM uses a technique of portioning the partial products into least significant part as well as most significant part.…”

Section: Architectures Of Multiplication Algorithmsmentioning

confidence: 99%

“…To reduce the number of multiplier bits, it used different recoding techniques such as radix-2, radix-4 and radix-8. Over the recent years, different researchers proposed different kind of architecture to perform booth multiplication with different speed, area occupation and power consumption [12], [13], [14], [15], [16], [17], [18], [19], [20], [21]. Among three parameters energy utilization and area occupation get more importance to fabricate chips for consumer electronic devices like mobile handset.…”

Section: Introductionmentioning

confidence: 99%

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VLSI Architectures of Booth Multiplication Algorithms – A Review

Hareesh¹,

C²,

Prasad³

2022

IJCDS

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The Booth multiplication scheme plays a major role in designing signed multiplier using multiplier encoder and by decreasing the number of intermediate products. Both radix-4 and radix-8 Booth encoding schemes are widely used due to simple and fast respectively. Multiplier is one of the basic as well as an important part in arithmetic unit of many high-performance operations like digital signal processing (DSP) and digital image processing (DIP) and other high-performance central processing unit (CPU) operation. In the past decade numerous ways of Booth multiplier circuits have been implemented by using different application specific integrated circuit (ASIC) technology like Taiwan semiconductor manufacturing technology (TSMC) 45 nm and 65 nm complementary metal oxide semiconductor (CMOS) process and some of the implementations have been proposed by field programmable gate array (FPGA). This work analyses the very large-scale integration (VLSI) characteristics such as area utilization, power consumption and speed of operation of different types of implementation of Booth multiplication scheme. Based on the exhaustive examination on Booth multiplication scheme, it is noticed that the recent implementation of approximate computing-based and modified two's complementor-based multiplication algorithms outperform other multiplication schemes. Further, the VLSI technology using ST Microelectronics (STM) 28 nm and TSMC 45 nm CMOS processes beat the other implantation schemes by providing less-area and power as well as high-speed of multiplication, respectively.

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Section: Architectures Of Multiplication Algorithmsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

VLSI Architectures of Booth Multiplication Algorithms – A Review

Hareesh¹,

C²,

Prasad³

2022

IJCDS

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“…Fig. 4 shows the hybrid carry array presented by [8]  Addition and subtraction operations may be done on two's complement and signs of inputs separated of one another  The static range is synchronous  Errors is simpler to detect However, wiring difficulties of two's complement have led to new modifications in array structures. Furthermore, dynamic CMOS implementation is required to design efficient structures, implying a three-stage compression process because the area reduction issue.…”

Section: Hybrid Additionmentioning

confidence: 99%

A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network

Asadi

2015

IJIEEB

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In this paper, a new multiplier is presented which uses modified fourteen transistor adder and optimized hybrid counter for partial product reduction step. Conventional adder is modified to improve Wallace tree functionality. Reducing critical path in counter structure can reduce VLSI area in whole multiplier structure. This paper uses a new structure in partial product reduction step to increase speed. Four to two compressors are used in modified Wallace structure to minimize the critical path. In final addition step of algorithm a new carry lookahead network is presented which adds two final operands efficiently. It uses dynamic CMOS in transistor level to reduce power consumption. Proposed multiplier reduces critical path, increases speed and decreases wiring problems in compare with previous algorithms efficiently. A new Booth encoder is presented in radix 16 circuitry. It decreases number of partial products while hardware overhead is minimized.

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“…Many papers [12], [13], [14] and [15] were focussed on the design of low power array multiplier. They followed signal flow optimization in [3:2] adder array for the linear partial product reduction, left-toright leapfrog (LRLF) structure and upper / lower splitting structure.…”

Section: Introductionmentioning

confidence: 99%

Design and VLSI Implementation of N X N Binary Multiplier Using Successive Approximation of (N-1) X (N-1) Binary Multipliers

2016

IJSR

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In VLSI technology, power consumption and delay becomes a major problem in multipliers. To reduce these issues we propose a new multiplier algorithm that combines numerical transformation and shift and add technique. In this design N X N bitmultiplication is done by using successive approximation of (N-1) X (N-1) bit multiplier. The strength of the multiplication is reduced by weight reduction technique.The performance of N-bit multiplier using successive approximation of N-1 bit multiplier is compared with the existing techniques and evaluated through simulation in order to highlight the speed superiority by reducing the number of components and interconnections. N-bit successive approximation is an excellent choice for low area and high speed applications. All the above mentioned multipliers are coded in VHDL and simulated in ModelSim and synthesized in EDA tool Xilinx_ISE 9.2i. This method is suitable for higher order bits. The analysis of power report is also presented here the proposed design is suitable for high speed, low area applications.

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Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)

Cited by 16 publications

References 31 publications

VLSI Architectures of Booth Multiplication Algorithms – A Review

VLSI Architectures of Booth Multiplication Algorithms – A Review

A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network

Design and VLSI Implementation of N X N Binary Multiplier Using Successive Approximation of (N-1) X (N-1) Binary Multipliers

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