2013
DOI: 10.1109/tcsi.2013.2248851
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Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)

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Cited by 16 publications
(6 citation statements)
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References 31 publications
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“…Chen et al 2013 designed and implemented an energy-efficient variable-latency speculating Booth multiplier (VLSBM) to increase the functionality in a gloomy process [19]. To reduce complexity the VLSBM uses a technique of portioning the partial products into least significant part as well as most significant part.…”
Section: Architectures Of Multiplication Algorithmsmentioning
confidence: 99%
See 1 more Smart Citation
“…Chen et al 2013 designed and implemented an energy-efficient variable-latency speculating Booth multiplier (VLSBM) to increase the functionality in a gloomy process [19]. To reduce complexity the VLSBM uses a technique of portioning the partial products into least significant part as well as most significant part.…”
Section: Architectures Of Multiplication Algorithmsmentioning
confidence: 99%
“…To reduce the number of multiplier bits, it used different recoding techniques such as radix-2, radix-4 and radix-8. Over the recent years, different researchers proposed different kind of architecture to perform booth multiplication with different speed, area occupation and power consumption [12], [13], [14], [15], [16], [17], [18], [19], [20], [21]. Among three parameters energy utilization and area occupation get more importance to fabricate chips for consumer electronic devices like mobile handset.…”
Section: Introductionmentioning
confidence: 99%
“…Fig. 4 shows the hybrid carry array presented by [8]  Addition and subtraction operations may be done on two's complement and signs of inputs separated of one another  The static range is synchronous  Errors is simpler to detect However, wiring difficulties of two's complement have led to new modifications in array structures. Furthermore, dynamic CMOS implementation is required to design efficient structures, implying a three-stage compression process because the area reduction issue.…”
Section: Hybrid Additionmentioning
confidence: 99%
“…Many papers [12], [13], [14] and [15] were focussed on the design of low power array multiplier. They followed signal flow optimization in [3:2] adder array for the linear partial product reduction, left-toright leapfrog (LRLF) structure and upper / lower splitting structure.…”
Section: Introductionmentioning
confidence: 99%