Abstract:In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modalism simulation software and would be revised until the simulation results become correct. Finally, the… Show more
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