Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression

Usami, Kimiyoshi; Shirai, Tomoyuki; Hashida, T.; Masuda, H.; Takeda, S.; Nakata, Masao; Seki, Naomi; Amano, Hideharu; Namiki, Mitaro; Imai, Masayuki; Kondo, Masaaki; Nakamura, Hiroshi

doi:10.1109/vlsi.design.2009.63

Cited by 25 publications

(13 citation statements)

References 5 publications

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“…All the functional units were assumed to have a bit width of 16. All the functional units, power switch [12], and BET were obtained by synthesizing them beforehand based on the CMOS 90 nm technology. Selectable voltages were assumed to v l = 0.8 V, v m = 1.0 V, and v h = 1.2 V. The clock period constraint was given to be 1.5 ns in all experiments.…”

Section: Resultsmentioning

confidence: 99%

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe

Shi

Usami

et al. 2013

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)

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In this paper, we propose an adaptive voltage huddlebased distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50% energy-saving compared with conventional algorithms.

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Section: Resultsmentioning

confidence: 99%

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe

Shi

Usami

et al. 2013

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)

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show abstract

“…9 for further evaluations. Specifically, we compare PART with the delay chain approach [8], [11]. As stated in the experimental setup, we use the peak current when SIMD is exercising its longest path to approximate the maximum active current.…”

Section: Performance Of Partmentioning

confidence: 99%

“…2(a)] into multiple ones [see Fig. 2(b)] and devise various strategies to turn on the power switches in a desired sequence [8], [10], [11]. As illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

Towards Process Variation-Aware Power Gating

Yeh

Chen

Wang

2012

IEEE Trans. VLSI Syst.

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This paper presents a power gating design that considers process variation for proper wakeup control. First, the surge current constraint is examined and refined for a simpler and more realistic view of inter-module reliability. Following that, several circuits are proposed on top of a delay chain to adapt the timing control of power switches to process variations. Experimental results show that the proposed design is able to track process variation such that the surge current and the wakeup time are both kept to expectation in all process corners.

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“…Alternatively, most techniques achieve this through a progressive wakeup, either by turning on different parts of the circuit consecutively, or by gradually increasing the gate voltage of the sleep device [4,10]. The end result is an effective reduction in the inrush current, but at the cost of an increased wakeup time.…”

Section: Introductionmentioning

confidence: 99%

CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits

Farah

Bayoumi

2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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Power gating can be a source of disturbances detrimental to IC robustness and response time. This work introduces Current-Equalized Multi-Stage Power Gating (CEMS-PG), a parameterized algorithm for finding an efficient wakeup approach given a maximum tolerable fluctuation in the power distribution network. Applying both partitioning and scheduling, CEMS-PG efficiently divides a power gated circuit into partitions with near-equal surge currents, making them suitable for an improved form of Staggered-Phase Damping. Our simulations show up to 44% improvement in wakeup time and 78% in peak noise, offering minimal compromise between the two.I.

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Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression

Cited by 25 publications

References 5 publications

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Towards Process Variation-Aware Power Gating

CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits

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