Design and implementation of counting networks

On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

“…State-of-the-art hardware implementations of popcount computations have been exhaustively analyzed in [26][27][28][29][30]. The results were presented in form of charts in [26,28,30] that compare the cost and the latency of four selected methods. The basic ideas of these methods are summarized below:…”

“…(3) Counting networks [28] eliminate propagation delays in carry chains that appear in [26] and give very good results especially for pipelined implementations. However, they occupy many general-purpose logical slices which are very extensively employed for the majority of practical applications frequently running parallel with popcount computations.…”

“…However, they are very resource consuming [32]. In [28] a similar technique was used for parallel vector processing with noncomparison operations. The proposed circuits are targeted mainly towards various counting operations and they are called counting networks.…”

“…In contrast to competitive designs based on parallel counters [26], counting networks do not involve a carry propagation chain needed for adders in [26]. Thus, the delays are reduced and this is clearly shown in [28]. The networks [28] are easily parameterizable and scalable allowing thousands of bits to be processed in combinational circuits.…”

“…Thus, the delays are reduced and this is clearly shown in [28]. The networks [28] are easily parameterizable and scalable allowing thousands of bits to be processed in combinational circuits. Besides, a pipeline can easily be created.…”