Design and Implementation of BIST

Patil, Manoj E; Sharanabasaveshwar, H B

doi:10.1109/iceeccot43722.2018.9001663

Cited by 6 publications

(3 citation statements)

References 5 publications

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“…A minimized scan chain consisting of only the TopCounter nodes could offer the precision of ATPG vectors without the need to serially scanin data to the over 34,000 nodes in Potato. Future work could investigate the process of mixing and chaining the TopCounter nodes into a "mini-scan-chain", as well as implementing a specialized BIST controller [25] that serially scans in the test vector and inspects the serial data output. These test vectors would likely be much shorter than those described in this work, while the BIST controller would likely consume minimal overhead due to only interacting with a handful of nodes.…”

Section: Next Stepsmentioning

confidence: 99%

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

Somoye,

Plusquellic,

Mannos

et al. 2024

Cryptography

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Recent evaluations of counter-based periodic testing strategies for fault detection in Microprocessor (μP) have shown that only a small set of counters is needed to provide complete coverage of severe faults. Severe faults are defined as faults that leak sensitive information, e.g., an encryption key on the output of a serial port. Alternatively, fault detection can be accomplished by executing instructions that periodically test the control and functional units of the μP. In this paper, we propose a fault detection method that utilizes an ’engineered’ executable program combined with a small set of strategically placed counters in pursuit of a hardware Periodic Built-In-Self-Test (PBIST). We analyze two distinct methods for generating such a binary; the first uses an Automatic Test Generation Pattern (ATPG)-based methodology, and the second uses a process whereby existing counter-based node-monitoring infrastructure is utilized. We show that complete fault coverage of all leakage faults is possible using relatively small binaries with low latency to fault detection and by utilizing only a few strategically placed counters in the μP.

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Section: Next Stepsmentioning

confidence: 99%

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

Somoye,

Plusquellic,

Mannos

et al. 2024

Cryptography

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“…II. LITERATURE REVIEW [3] illustrates the conception and execution of BIST utilizing the traditional SISR and LFSR. BS approach for low-power BIST is presented in [6], which may decline power utilization by up to 25% when comparing the traditional approach utilized in [3].…”

Section: Introductionmentioning

confidence: 99%

“…LITERATURE REVIEW [3] illustrates the conception and execution of BIST utilizing the traditional SISR and LFSR. BS approach for low-power BIST is presented in [6], which may decline power utilization by up to 25% when comparing the traditional approach utilized in [3]. By applying BS-LFSR with scan-chain reordering, peak power, as well as average power may both be reduced by up to 65 and 55 percent, correspondingly [7].…”

Section: Introductionmentioning

confidence: 99%

Designing and Implementing a power Efficient BIST in a BCD Multiplier

SAM¹

2022

Preprint

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<p> On any chip, the number of transistors doubles every eighteen months according to Moore's law. When there are more transistors in a circuit, there is a higher probability that one of those transistors will have a fault. To avoid and detect possible errors,testing is required. To test the required circuit, the BIST (Built-in-Self-Test) energy saving design emplos a modified MISR as the ORA (Output Response Analyzer) and a bit-swapping LFSR as the TPG (Test Pattern Generator). In this paper, we select two circuits - a combined circuit and an 8x8 BCD multiplier as CUT (circuit under test). TPG generates test patters that are fed into CUT, hile ORA evaluates the data generated by CUT and checks for errors in the circuit, and generates a pass/fail signal. This BIST structure detects one of the errors in the circuit.All results are matched to Xilinx ISE Design Suite 14.7 using Verilog and integrated into Vivado 2018.2.<br> </p>

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